component
CY95F636KPMC-G-UNE2
Public Made by Adomby adom
Cypress Semicon CYPRESS, LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Contents
README
markdownCY95F636KPMC-G-UNE2
Cypress Semicon · CYPRESS · LQFP-32(7x7)
CY95F636KPMC-G-UNE2 from Cypress Semicon, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PG2/X1A/SNI2 | bidirectional | General-purpose I/O port that doubles as the subclock I/O oscillation pin (X1A) and the MPG waveform sequencer position-detection trigger input (SNI2), with hysteresis CMOS input. |
| 2 | PG1/X0A/SNI1 | bidirectional | General-purpose I/O port that doubles as the subclock input oscillation pin (X0A) and the MPG waveform sequencer position-detection trigger input (SNI1), with hysteresis CMOS input. |
| 3 | VCC | power_in | Power supply pin; the datasheet requires a minimum of 2.4 V in normal operation and a maximum of 5.5 V. |
| 4 | C | passive | Decoupling capacitor connection pin, which requires a ceramic capacitor of 0.022 µF to 1 µF (CS) connected to VSS. |
| 5 | P67/PPG21/TRG1/OPT5 | bidirectional | High-current general-purpose I/O port that also serves as 8/16-bit PPG ch.2 output, 16-bit PPG timer ch.1 trigger input and MPG waveform sequencer output, with hysteresis CMOS input. |
| 6 | P66/PPG20/PPG1/OPT4 | bidirectional | High-current general-purpose I/O port that also serves as 8/16-bit PPG ch.2 output, 16-bit PPG timer ch.1 output and MPG waveform sequencer output, with hysteresis CMOS input. |
| 7 | P65/PPG11/OPT3 | bidirectional | High-current general-purpose I/O port that also serves as 8/16-bit PPG ch.1 output and MPG waveform sequencer output, with hysteresis CMOS input. |
| 8 | P64/EC1/PPG10/OPT2 | bidirectional | High-current general-purpose I/O port that also serves as 8/16-bit composite timer ch.1 clock input (EC1), 8/16-bit PPG ch.1 output and MPG waveform sequencer output, with hysteresis CMOS input. |
| 9 | P63/TO11/PPG01/OPT1 | bidirectional | High-current general-purpose I/O port that also serves as 8/16-bit composite timer ch.1 output (TO11), 8/16-bit PPG ch.0 output and MPG waveform sequencer output, with hysteresis CMOS input. |
| 10 | P62/TO10/PPG00/OPT0 | bidirectional | High-current general-purpose I/O port that also serves as 8/16-bit composite timer ch.1 output (TO10), 8/16-bit PPG ch.0 output and MPG waveform sequencer output, with hysteresis CMOS input. |
| 11 | P61/INT09/SCL/TI1 | bidirectional | General-purpose I/O port that also serves as external interrupt input INT09, I2C bus interface ch.0 clock I/O (SCL) and 16-bit reload timer ch.1 input (TI1), with CMOS input level. |
| 12 | P60/INT08/SDA/DTTI | bidirectional | General-purpose I/O port that also serves as external interrupt input INT08, I2C bus interface ch.0 data I/O (SDA) and MPG waveform sequencer input (DTTI), with CMOS input level. |
| 13 | P00/INT00/AN00/CMP0_P | bidirectional | General-purpose I/O port that also serves as external interrupt input INT00, 8/10-bit A/D converter analog input AN00 and comparator non-inverting input CMP0_P, with hysteresis/analog input. |
| 14 | P01/INT01/AN01/CMP0_N | bidirectional | General-purpose I/O port that also serves as external interrupt input INT01, 8/10-bit A/D converter analog input AN01 and comparator inverting input CMP0_N, with hysteresis/analog input. |
| 15 | P02/INT02/AN02/SCK | bidirectional | General-purpose I/O port that also serves as external interrupt input INT02, 8/10-bit A/D converter analog input AN02 and LIN-UART clock I/O (SCK), with hysteresis/analog input. |
| 16 | P03/INT03/AN03/SOT | bidirectional | General-purpose I/O port that also serves as external interrupt input INT03, 8/10-bit A/D converter analog input AN03 and LIN-UART data output (SOT), with hysteresis/analog input. |
| 17 | P04/INT04/AN04/SIN/EC0 | bidirectional | General-purpose I/O port that also serves as external interrupt input INT04, 8/10-bit A/D converter analog input AN04, LIN-UART data input (SIN) and 8/16-bit composite timer ch.0 clock input (EC0), with CMOS/analog input. |
| 18 | P05/INT05/AN05/TO00 | bidirectional | General-purpose I/O port that also serves as external interrupt input INT05, 8/10-bit A/D converter analog input AN05 and 8/16-bit composite timer ch.0 output (TO00), with hysteresis/analog input. |
| 19 | P06/INT06/AN06/TO01 | bidirectional | General-purpose I/O port that also serves as external interrupt input INT06, 8/10-bit A/D converter analog input AN06 and 8/16-bit composite timer ch.0 output (TO01), with hysteresis/analog input. |
| 20 | P07/INT07/AN07 | bidirectional | General-purpose I/O port that also serves as external interrupt input INT07 and 8/10-bit A/D converter analog input AN07, with hysteresis/analog input. |
| 21 | P10/PPG10/CMP0_O | bidirectional | General-purpose I/O port that also serves as 8/16-bit PPG ch.1 output (PPG10) and comparator digital output (CMP0_O), with hysteresis CMOS input. |
| 22 | P11/PPG11 | bidirectional | General-purpose I/O port that also serves as 8/16-bit PPG ch.1 output (PPG11), with hysteresis CMOS input. |
| 23 | P12/DBG/EC0 | bidirectional | N-ch open-drain general-purpose I/O port that also serves as the DBG debug input pin and 8/16-bit composite timer ch.0 clock input (EC0), and requires an external pull-up of 2 kΩ or above. |
| 24 | P13/PPG00 | bidirectional | General-purpose I/O port that also serves as 8/16-bit PPG ch.0 output (PPG00), with hysteresis CMOS input. |
| 25 | P14/UCK0/PPG01 | bidirectional | General-purpose I/O port that also serves as UART/SIO ch.0 clock I/O (UCK0) and 8/16-bit PPG ch.0 output (PPG01), with hysteresis CMOS input. |
| 26 | P15/UO0/PPG20 | bidirectional | General-purpose I/O port that also serves as UART/SIO ch.0 data output (UO0) and 8/16-bit PPG ch.2 output (PPG20), with hysteresis CMOS input. |
| 27 | P16/UI0/PPG21 | bidirectional | General-purpose I/O port that also serves as UART/SIO ch.0 data input (UI0) and 8/16-bit PPG ch.2 output (PPG21), with CMOS input level. |
| 28 | P17/TO1/SNI0 | bidirectional | General-purpose I/O port that also serves as 16-bit reload timer ch.1 output (TO1) and MPG waveform sequencer position-detection trigger input (SNI0), with hysteresis CMOS input. |
| 29 | PF2/RST | bidirectional | N-ch open-drain pin that functions as the reset input/output after power-on, with reset output enabled by the RSTOE bit and reset input or general-purpose I/O selected by the RSTEN bit in the SYSC register, and requires an external pull-up of 2 kΩ or above. |
| 30 | PF0/X0 | input | General-purpose I/O port that serves as the main clock input oscillation pin (X0), with hysteresis CMOS input. |
| 31 | PF1/X1 | bidirectional | General-purpose I/O port that serves as the main clock I/O oscillation pin (X1), with hysteresis CMOS input. |
| 32 | VSS | power_in | Ground pin (GND) that must be connected to the power supply ground with low impedance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature | TA | -40 | 85 | C | Other than on-chip debug mode | 63 | |
| Operating temperature (on-chip debug) | TA | 5 | 35 | C | On-chip debug mode | 63 | |
| Power supply voltage | VCC | 2.4 | 5.5 | V | In normal operation | 63 | |
| Power supply voltage (hold in stop mode) | VCC | 2.3 | 5.5 | V | Hold condition in stop mode | 63 | |
| Decoupling capacitor | CS | 0.022 | 1 | µF | 63 | ||
| Power supply voltage | VCC | 6 | V | VSS-0.3 V to VSS+6 V; VSS = 0.0 V | 61 | ||
| Input voltage | VI | 6 | V | VSS-0.3 V to VSS+6 V | 61 | ||
| Output voltage | VO | 6 | V | VSS-0.3 V to VSS+6 V | 61 | ||
| Maximum clamp current | ICLAMP | 2 | mA | Applicable to specific pins | 61 | ||
| Total maximum clamp current | /ICLAMP/ | 20 | mA | Applicable to specific pins | 61 | ||
| L level maximum output current | IOL | 15 | mA | 61 | |||
| L level average current (other than P62 to P67) | IOLAV1 | 4 | mA | Other than P62 to P67; average output current = operating current x operating ratio (1 pin) | 61 | ||
| L level average output current (P62 to P67) | IOLAV2 | 12 | mA | P62 to P67; average output current = operating current x operating ratio (1 pin) | 61 | ||
| L level total maximum output current | IOL | 100 | mA | 61 | |||
| L level total average output current | IOLAV | 37 | mA | Total average output current = operating current x operating ratio (total number of pins) | 61 | ||
| H level maximum output current | IOH | 15 | mA | 61 | |||
| H level average current (other than P62 to P67) | IOHAV1 | 4 | mA | Other than P62 to P67; average output current = operating current x operating ratio (1 pin) | 61 | ||
| H level average output current (P62 to P67) | IOHAV2 | 8 | mA | P62 to P67; average output current = operating current x operating ratio (1 pin) | 61 | ||
| H level total maximum output current | IOH | 100 | mA | 61 | |||
| H level total average output current | IOHAV | 47 | mA | Total average output current = operating current x operating ratio (total number of pins) | 61 | ||
| Power consumption | Pd | 320 | mW | 61 | |||
| Operating temperature | TA | -40 | 85 | C | 61 | ||
| Storage temperature | Tstg | -55 | 150 | C | 61 | ||
| Input leak current | ILI | -5 | 5 | µA | 0.0 V < VI < VCC; when the internal pull-up resistor is disabled | 64 | |
| Open-drain output application voltage | VD | 5.5 | V | P12, P60, P61, PF2; VCC = 5.0 V ±10% | 64 | ||
| Internal pull-up resistor | RPULL | 25 | 50 | 100 | kΩ | VI = 0 V; when the internal pull-up resistor is enabled | 64 |
| Input capacitance | CIN | 5 | 15 | pF | Other than VCC and VSS; f = 1 MHz | 64 | |
| Power supply current (external clock, main clock mode) | ICC | 3.6 | 5.8 | mA | FCH = 32 MHz, FMP = 16 MHz, divided by 2; except during Flash programming and erasing | 65 | |
| Power supply current (during Flash programming/erasing) | ICC | 7.5 | 13.8 | mA | FCH = 32 MHz, FMP = 16 MHz; during Flash memory programming and erasing | 65 | |
| Power supply current (at A/D conversion) | ICC | 4.1 | 9.1 | mA | At A/D conversion | 65 | |
| Power supply current (main sleep mode) | ICCS | 1.3 | 3 | mA | FCH = 32 MHz, FMP = 16 MHz; main sleep mode (divided by 2) | 65 | |
| Power supply current (subclock mode) | ICCL | 49 | 145 | µA | FCL = 32 kHz, FMPL = 16 kHz; TA = 25°C | 65 | |
| Power supply current (subsleep mode, deep standby) | ICCLS | 10 | 15 | µA | FCL = 32 kHz, FMPL = 16 kHz; TA = 25°C; in deep standby mode | 65 | |
| Power supply current (watch mode, deep standby) | ICCT | 7 | 13 | µA | FCL = 32 kHz; TA = 25°C; in deep standby mode | 65 | |
| Power supply current (main CR PLL clock mode) | ICCMPLL | 4.7 | 6.8 | mA | FMCRPLL = 16 MHz, FMP = 16 MHz; multiplied by 4; TA = 25°C | 65 | |
| Power supply current (main CR clock mode) | ICCMCR | 1.1 | 4.6 | mA | FCRH = 4 MHz, FMP = 4 MHz | 65 | |
| Power supply current (sub-CR clock mode) | ICCSCR | 58.1 | 230 | µA | Sub-CR clock mode (divided by 2); TA = 25°C | 65 | |
| Power supply current (time-base timer mode, deep standby) | ICCTS | 345 | 395 | µA | FCH = 32 MHz; time-base timer mode; TA = 25°C; in deep standby mode | 65 | |
| Current consumption of the comparator | IV | 60 | 160 | µA | 66 | ||
| Current consumption of the low-voltage detection circuit | ILVD | 4 | 7 | µA | 66 | ||
| Current consumption of the main CR oscillator | ICRH | 240 | 320 | µA | 66 | ||
| Current consumption of the sub-CR oscillator | ICRL | 7 | 20 | µA | Oscillating at 100 kHz | 66 | |
| Current consumption difference between normal standby and deep standby | INSTBY | 20 | 30 | µA | TA = 25°C | 66 | |
| Clock frequency (main oscillation, crystal/resonator) | FCH | 1 | 16.25 | MHz | When the main oscillation circuit is used | 67 | |
| Clock frequency (main external clock) | FCH | 1 | 32.5 | MHz | When the main external clock is used | 67 | |
| Clock frequency (main CR clock, 0°C to 70°C) | FCRH | 3.92 | 4 | 4.08 | MHz | Main CR clock used; 0°C ≤ TA ≤ 70°C | 67 |
| Clock frequency (main CR clock, -40°C to 85°C) | FCRH | 3.8 | 4 | 4.2 | MHz | Main CR clock used; -40°C ≤ TA ≤ 0°C, 70°C ≤ TA ≤ 85°C | 67 |
| Clock frequency (sub-CR clock) | FCRL | 50 | 100 | 150 | kHz | When the sub-CR clock is used | 67 |
| Clock cycle time (main oscillation circuit) | tHCYL | 61.5 | 1000 | ns | When the main oscillation circuit is used | 68 | |
| Clock cycle time (external clock) | tHCYL | 30.8 | 1000 | ns | When an external clock is used | 68 | |
| Source clock frequency (main oscillation clock) | FSP | 0.5 | 16.25 | MHz | When the main oscillation clock is used | 70 | |
| Resolution | 10 | bit | A/D converter | 85 | |||
| Total error | -3 | 3 | LSB | A/D converter | 85 | ||
| Linearity error | -2.5 | 2.5 | LSB | A/D converter | 85 | ||
| Differential linearity error | -1.9 | 1.9 | LSB | A/D converter | 85 | ||
| Flash sector erase time (2 Kbyte sector) | 0.3 | 1.6 | s | Time of writing 0x00 prior to erasure excluded; max at VCC = 2.4 V, TA = 85°C, 100000 cycles | 89 | ||
| Flash sector erase time (32 Kbyte sector) | 0.6 | 3.1 | s | Time of writing 0x00 prior to erasure excluded; max at VCC = 2.4 V, TA = 85°C, 100000 cycles | 89 | ||
| Byte writing time | 17 | 272 | µs | System-level overhead excluded | 89 | ||
| Program/erase cycle | 100000 | cycle | 89 | ||||
| Power supply voltage at program/erase | VCC | 2.4 | 5.5 | V | 89 | ||
| Flash memory data retention time | 20 | year | Average TA = 85°C; number of program/erase cycles 1000 or below | 89 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, | 16 |
CAD (KiCad official)
- Symbol:
CY95F636KPMC-G-UNE2 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
cy95f636kpmc-g-une2-etched.step/cy95f636kpmc-g-une2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy95f636kpmc-g-une2.step/cy95f636kpmc-g-une2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (102 pp, sha256
4e2eab7c3ba8c56e, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).