component
ACPL-C790-500E
Public Made by Adomby adom
Broadcom AVAGO Operational Amplifier, SO-8-6.8mm. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownACPL-C790-500E
Broadcom AVAGO · Operational Amplifier · SO-8-6.8mm
ACPL-C790-500E from Broadcom AVAGO, in a SO-8-6.8mm. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Input-side supply voltage, 4.5 V to 5.5 V referenced to GND1. Requires a 0.1 µF bypass capacitor between pins 1 and 4. Typical input-side supply current IDD1 = 11 mA (18.5 mA max). |
| 2 | VIN+ | input | Positive analog input. Nominal input range ±200 mV (full-scale ±300 mV, functional ±2 V) relative to VIN-. Input bias current typ. -0.1 µA; single-ended input impedance 27 kΩ. |
| 3 | VIN- | input | Negative analog input, normally connected to GND1 for single-ended sensing. Same ±200 mV nominal range and 27 kΩ single-ended input impedance as VIN+. |
| 4 | GND1 | power_in | Input-side ground reference for VDD1, VIN+ and VIN-. |
| 5 | GND2 | power_in | Output-side ground reference for VDD2, VOUT+ and VOUT-. Galvanically isolated from GND1 by the optical barrier (VIORM = 1414 Vpeak, 5000 Vrms/1 min). |
| 6 | VOUT- | output | Negative differential analog output. Output common-mode voltage 1.23 V, output voltage range 0 V to 2.5 V, output resistance ~21 Ω, short-circuit current ~11 mA. |
| 7 | VOUT+ | output | Positive differential analog output. Output common-mode voltage 1.23 V, output voltage range 0 V to 2.5 V, output resistance ~21 Ω, short-circuit current ~11 mA. |
| 8 | VDD2 | power_in | Output-side supply voltage, 3 V to 5.5 V referenced to GND2. Requires a 0.1 µF bypass capacitor between pins 5 and 8. Typical IDD2 = 7 mA at 5 V (6.8 mA at 3.3 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Broadcom AVAGO |
| Package | SO-8-6.8mm |
| Category | Op-amp/Cmp |
| Pins | 8 |
Ordering variants
ACPL-C790-500EACPL-C790-500E-000E
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS | -1 | 0.4 | 2 | mV | TA = 25°C | 6 |
| Magnitude of Input Offset Change vs. Temperature (absolute value) | /dVOS/dTA/ | -0.8 | 4 | µV/°C | TA = –40°C to +105°C; absolute value | 6 | |
| Gain (ACPL-C790, ±3%) | G3 | 7.95 | 8.2 | 8.44 | V/V | TA = 25°C; Note 2 | 6 |
| Magnitude of Gain Change vs. Temperature | dG/dTA | -0.00041 | V/V/°C | TA = –40°C to +105°C; Note 3 | 6 | ||
| Nonlinearity over ±200 mV Input Voltage | NL200 | 0.05 | 0.13 | % | VIN+ = –200 mV to +200 mV, TA = 25°C; Note 2 | 6 | |
| Magnitude of NL200 Change vs. Temperature | dNL200/dTA | 0.0003 | %/°C | TA = –40°C to +105°C | 6 | ||
| Nonlinearity over ±100 mV Input Voltage | NL100 | 0.013 | 0.06 | % | VIN+ = –100 mV to +100 mV, TA = 25°C; Note 2 | 6 | |
| Full-Scale Differential Voltage Input Range | FSR | -300 | 300 | mV | VIN = VIN+ – VIN–; Note 4 | 6 | |
| Input Bias Current | IIN+ | -1 | -0.1 | µA | VIN+ = 0 V, VIN– = 0 V; Note 5 | 6 | |
| Magnitude of IIN+ Change vs. Temperature | dIIN+/dTA | -0.05 | nA/°C | 6 | |||
| Equivalent Input Impedance | RIN | 27 | kΩ | VIN+ or VIN–, single-ended | 6 | ||
| Output Common-Mode Voltage | VOCM | 1.23 | V | VOUT+ or VOUT–; Note 6 | 6 | ||
| Output Voltage Range | OVR | 0 | 2.5 | V | VOUT+ or VOUT–; Note 4 | 6 | |
| Output Short-Circuit Current | /IOSC/ | 11 | mA | VOUT+ or VOUT–, shorted to GND2 or VDD2 | 6 | ||
| Output Resistance | ROUT | 21 | Ω | VOUT+ or VOUT– | 6 | ||
| Input DC Common-Mode Rejection Ratio | CMRRIN | 76 | dB | Note 2 | 6 | ||
| Signal-to-Noise Ratio | SNR | 62 | dB | VIN+ = 300 mVpp 10 kHz sine wave; Note 7 | 6 | ||
| Signal-to-(Noise + Distortion) Ratio | SNDR | 59 | dB | VIN+ = 300 mVpp 10 kHz sine wave; Note 8 | 6 | ||
| Small-Signal Bandwidth (-3 dB) | f–3dB | 140 | 200 | kHz | 6 | ||
| Input to Output Propagation Delay (10%-10%) | tPD10 | 1.6 | 2.3 | µs | 200 mV/µs step input | 6 | |
| Input to Output Propagation Delay (50%-50%) | tPD50 | 2 | 2.6 | µs | 200 mV/µs step input | 6 | |
| Input to Output Propagation Delay (90%-90%) | tPD90 | 2.6 | 3.3 | µs | 200 mV/µs step input | 6 | |
| Output Rise/Fall Time (10%-90%) | tR/F | 1.7 | µs | Step input | 6 | ||
| Common Mode Transient Immunity | CMTI | 10 | 15 | kV/μs | VCM = 1 kV, TA = 25°C; Note 2 | 6 | |
| Power Supply Rejection | PSR | -78 | dB | 1 Vpp 1 kHz sine wave ripple on VDD1, differential output; Note 9 | 6 | ||
| Input Side Supply Current | IDD1 | 11 | 18.5 | mA | VIN+ = 400 mV; see Note 10 | 6 | |
| Output Side Supply Current (5 V supply) | IDD2 | 7 | 12 | mA | 5 V supply | 6 | |
| Output Side Supply Current (3.3 V supply) | IDD2 | 6.8 | 11 | mA | 3.3 V supply | 6 | |
| Storage Temperature | TS | -55 | 125 | °C | 5 | ||
| Ambient Operating Temperature | TA | -40 | 105 | °C | 5 | ||
| Supply Voltages | VDD1, VDD2 | -0.5 | 6 | V | 5 | ||
| Steady-State Input Voltage | VIN+, VIN– | -2 | V | Note 1, 3; max printed as VDD1 + 0.5 | 5 | ||
| Two-Second Transient Input Voltage | VIN+, VIN– | -6 | V | Note 2; max printed as VDD1 + 0.5 | 5 | ||
| Output Voltages | VOUT+, VOUT– | -0.5 | V | max printed as VDD2 + 0.5 | 5 | ||
| Lead Solder Temperature | 260 | °C | 10 sec., 1.6 mm below seating plane | 5 | |||
| Ambient Operating Temperature | TA | -40 | 105 | °C | 5 | ||
| VDD1 Supply Voltage | VDD1 | 4.5 | 5.5 | V | 5 | ||
| VDD2 Supply Voltage | VDD2 | 3 | 5.5 | V | 5 | ||
| Input Voltage Range | VIN+, VIN– | -200 | 200 | mV | Note 1 (±200 mV nominal input range) | 5 |
CAD (KiCad official)
- Symbol:
ACPL-C790-500E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8-6.8mm (KiCad packages3D, STEP)
- 3D model files:
acpl-c790-500e-etched.step/acpl-c790-500e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);acpl-c790-500e.step/acpl-c790-500e.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
acpl-c790-500e.step |
122 KB | You want the bare part, or you mark your own boards. |
acpl-c790-500e-etched.step |
2.5 MB | You want the part with ACPL-C790-500E already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 618 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Broadcom AVAGO datasheet (14 pp, sha256
c0ffd6a7460a5a47, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).