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ACPL-C790-500E

Public Made by Adom

by adom

Broadcom AVAGO Operational Amplifier, SO-8-6.8mm. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs acpl-c790-500e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
acpl-c790-500e-etched.fit.json acpl-c790-500e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
acpl-c790-500e-etched.glb acpl-c790-500e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
acpl-c790-500e-etched.step acpl-c790-500e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
acpl-c790-500e.glb Publish 0.1.0 · Ray 1mo ago
acpl-c790-500e.kicad_mod Publish 0.1.0 · Ray 1mo ago
acpl-c790-500e.kicad_sym Publish 0.1.0 · Ray 1mo ago
acpl-c790-500e.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
acpl-c790-500e.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json acpl-c790-500e: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 16h ago
README.md acpl-c790-500e: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 20d ago

ACPL-C790-500E

Broadcom AVAGO · Operational Amplifier · SO-8-6.8mm

ACPL-C790-500E from Broadcom AVAGO, in a SO-8-6.8mm. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Input-side supply voltage, 4.5 V to 5.5 V referenced to GND1. Requires a 0.1 µF bypass capacitor between pins 1 and 4. Typical input-side supply current IDD1 = 11 mA (18.5 mA max).
2 VIN+ input Positive analog input. Nominal input range ±200 mV (full-scale ±300 mV, functional ±2 V) relative to VIN-. Input bias current typ. -0.1 µA; single-ended input impedance 27 kΩ.
3 VIN- input Negative analog input, normally connected to GND1 for single-ended sensing. Same ±200 mV nominal range and 27 kΩ single-ended input impedance as VIN+.
4 GND1 power_in Input-side ground reference for VDD1, VIN+ and VIN-.
5 GND2 power_in Output-side ground reference for VDD2, VOUT+ and VOUT-. Galvanically isolated from GND1 by the optical barrier (VIORM = 1414 Vpeak, 5000 Vrms/1 min).
6 VOUT- output Negative differential analog output. Output common-mode voltage 1.23 V, output voltage range 0 V to 2.5 V, output resistance ~21 Ω, short-circuit current ~11 mA.
7 VOUT+ output Positive differential analog output. Output common-mode voltage 1.23 V, output voltage range 0 V to 2.5 V, output resistance ~21 Ω, short-circuit current ~11 mA.
8 VDD2 power_in Output-side supply voltage, 3 V to 5.5 V referenced to GND2. Requires a 0.1 µF bypass capacitor between pins 5 and 8. Typical IDD2 = 7 mA at 5 V (6.8 mA at 3.3 V).

Key specifications

Parameter Value
Manufacturer Broadcom AVAGO
Package SO-8-6.8mm
Category Op-amp/Cmp
Pins 8

Ordering variants

  • ACPL-C790-500E
  • ACPL-C790-500E-000E

CAD (KiCad official)

  • Symbol: ACPL-C790-500E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8-6.8mm (KiCad packages3D, STEP)
  • 3D model files: acpl-c790-500e-etched.step / acpl-c790-500e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); acpl-c790-500e.step / acpl-c790-500e.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
acpl-c790-500e.step 122 KB You want the bare part, or you mark your own boards.
acpl-c790-500e-etched.step 2.5 MB You want the part with ACPL-C790-500E already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 618 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Broadcom AVAGO datasheet (14 pp, sha256 c0ffd6a7460a5a47, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF