component
PD70101ILQ-TR
Public Made by Adomby adom
Microchip Tech Power Over Ethernet (PoE) Controllers, QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPD70101ILQ-TR
Microchip Tech · Power Over Ethernet (PoE) Controllers · QFN-32(5x5)
PD70101ILQ-TR from Microchip Tech, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RDET | passive | Connect a 24.9 kΩ, 1% detection resistor from this pin to VPP. |
| 2 | PGOOD | output | Open-drain active-low output that flags the power rails (VPN_OUT) are ready, with the MOSFET rated for 5 mA and pull-up to VPP. |
| 3 | RREF | passive | Connect a 240k 1% bias resistor between this pin and VPN_IN for the PD interface. |
| 4 | RCLASS | passive | Connect an external classification resistor between this pin and VPN_IN to set the power class. |
| 5 | VPN_IN | power_in | VPort negative input connected to the isolation switch N-channel MOSFET source. |
| 6 | N/C | unconnected | Not used. |
| 7 | N/C | unconnected | Not used on PD70101; AT_FLAG open-drain output (active low) is a PD70201 function. |
| 8 | VPN_OUT | power_out | VPort negative output connected to the isolation switch output and N-channel MOSFET drain. |
| 9 | N/C | unconnected | Not used. |
| 10 | ENABLE | input | Logic-level enable input for the DC-DC controller, turned on by pulling this pin to VL, with thresholds VHI 2.0 V and VLO 0.8 V. |
| 11 | VINS | input | VPP input voltage sensing for the UVLO comparator, connected through an external divider from VPP to GND with a 1.2 V threshold. |
| 12 | HYST | passive | Output of the VINS/UVLO comparator used to program VPP UVLO hysteresis. |
| 13 | SYNC | input | External clock synchronization input that sets the DC-DC switching frequency to the applied clock. |
| 14 | RFREQ | passive | Connect a resistor from this pin to GND to set the DC-DC switching frequency. |
| 15 | SS | passive | Connect a capacitor from this pin to GND to set the DC-DC soft-start time, charged to 1.2 V. |
| 16 | RCLP | passive | Connect a resistor to GND to program the low power mode clamp voltage, or tie to GND to disable LPM. |
| 17 | VSN | input | Negative input of the differential amplifier, connected to the resistor divider junction from Vo- to GND. |
| 18 | VSP | input | Positive input of the differential amplifier, connected to the resistor divider junction from Vo+ to GND. |
| 19 | COMP | output | Error amplifier output, shorted to FB for isolated converters or connected to FB via RC compensation for non-isolated converters. |
| 20 | DAO | output | Differential amplifier output, connected to FB externally for non-isolated direct buck converter. |
| 21 | FB | input | Inverting input of the error amplifier, connected to the optocoupler for isolated DC-DC or to RC compensation for non-isolated DC-DC. |
| 22 | GND | power_in | Analog ground, connected to a local AGND plane with the soft-start capacitor and frequency resistor returned to it. |
| 23 | VL | power_out | 5 V (GND referenced) internal LDO output that requires a 1 µF or higher ceramic capacitor to GND. |
| 24 | SG | output | Secondary gate driver output, the complement of PG, left open if unused and low in low power skip mode. |
| 25 | PGND | power_in | Power ground connected to a local PGND plane for VCC decoupling, PG and SG drivers, and the primary current sense return. |
| 26 | CSN | input | Negative input of the current sense amplifier, Kelvin connected to the PGND side of the primary current sense resistor. |
| 27 | CSP | input | Positive input of the current sense amplifier, Kelvin connected to the non-PGND side of the primary current sense resistor. |
| 28 | PG | output | Primary gate driver output connected to the gate of the primary side power MOSFET, directly or via a resistor. |
| 29 | VH | power_out | 5 V high-side (VCC referenced) internal LDO output that requires a 0.1 µF or higher ceramic capacitor to VCC. |
| 30 | VCC | power_in | Input supply to the DC-DC controller that requires a 4.7 µF or higher ceramic capacitor to PGND. |
| 31 | VAUX | power_out | Auxiliary voltage reference to VPN_OUT used for DC-DC start-up, connected directly to VCC for PoE-only power or through a 30 V schottky diode for multiple sources. |
| 32 | VPP | power_in | Positive terminal of the PoE input port, connected to the positive terminal of the input bridges on the CDET positive side. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VPP, RDET, VPN_OUT (with respect to VPN_IN) | -0.3 | 74 | VDC | 7 | |||
| RREF, RCLASS (with respect to VPN_IN) | -0.3 | 6 | V | 7 | |||
| PGOOD, AT_FLAG, VAUX (with respect to VPN_OUT) | -0.3 | 74 | V | 7 | |||
| VCC (with respect to PGND) | VCC | -0.3 | 40 | VDC | 7 | ||
| PG, SG (with respect to PGND) | -0.3 | 20 | VDC | 7 | |||
| VL, VSN, VSP (with respect to PGND) | -0.3 | 6 | V | 7 | |||
| VH (with respect to VCC) | VH | -0.3 | VDC | 7 | |||
| All other pins (with respect to GND) | -0.3 | VDC | 7 | ||||
| ESD (HBM) protection at all I/O pins | -1 | 1 | kV | Pins 2 and 31 are ±150 V HBM | 7 | ||
| Maximum junction temperature (TJMAX) | TJMAX | 150 | °C | 7 | |||
| Operational ambient temperature | -40 | 85 | °C | 7 | |||
| Storage temperature range | -65 | 150 | °C | 7 | |||
| Peak package solder re-flow temperature | 260 | °C | 40 seconds maximum exposure, MSL3 | 7 | |||
| Junction to case thermal resistance | θJC | 5 | °C/W | No forced airflow; four-layer JESD-51 board | 7 | ||
| Junction to pad thermal resistance | θJP | 4 | °C/W | No forced airflow; four-layer JESD-51 board | 7 | ||
| Junction to ambient thermal resistance | θJA | 23 | °C/W | No forced airflow; four-layer JESD-51 board | 7 | ||
| Input voltage | VPP | 0 | 55 | 57 | V | 8 | |
| Detection voltage range | DETRANGE | 1.3 | 10.1 | V | Measured between VPP and VPN IN | 8 | |
| Detection switch ON resistance | RDET-ON | 50 | Ω | 2.5V ≤ (ΔVPP to VPNIN) ≤ 10.1 V; measured between RDET and VPN IN | 8 | ||
| Detection is disconnected | VDET-OFF | 10.1 | 12.8 | V | Measured between VPP and VPN IN | 8 | |
| Detection switch OFF resistance | RDET-OFF | 2 | MΩ | 12.8 V ≤ (ΔVPP to VPNIN) ≤ 57.0 V; measured between RDET and VPNIN | 8 | ||
| Input offset current | IOFFSET | 16 | µA | 2.5 V ≤ VPP ≤ 10.1 V; -40 °C ≤ TJ ≤ 85 °C | 8 | ||
| Input offset current | IOFFSET | 10 | µA | 2.5 V ≤ VPP ≤ 10.1 V; -40 °C ≤ TJ ≤ 55 °C | 8 | ||
| RDET reconnection level | VRDET-ON | 1.95 | 3 | 4.85 | V | Measured between VPP and VPNIN | 8 |
| Classification current source, turn ON threshold range | VTH-LOW-ON | 11.4 | 13.7 | V | Measured at VPP; turn on for any ICLASS while VPP increases | 9 | |
| Classification disconnection minimum hysteresis voltage | VHST | 1 | V | Hysteresis between VTH-low-on and VTH-low-off | 9 | ||
| Classification current source, turn OFF threshold range | VTH-HIGH-OFF | 20.9 | 23.9 | V | Measured at VPP; turn off while VPP increases | 9 | |
| Current limit threshold | ICLASS-LIM | 50 | 68 | 80 | mA | 9 | |
| Input current IPP when classification function is enabled, Class 1 | ICLASS-EN | 9.5 | 10.5 | 11.5 | mA | Class 1 RCLASS = 133 Ω ±1% | 9 |
| Input current IPP when classification function is enabled, Class 2 | ICLASS-EN | 17.5 | 18.5 | 19.5 | mA | Class 2 RCLASS = 69.8 Ω ±1% | 9 |
| Input current IPP when classification function is enabled, Class 3 | ICLASS-EN | 26.5 | 28 | 29.5 | mA | Class 3 RCLASS = 45.3 Ω ±1% | 9 |
| Input current IPP when classification function is enabled, Class 4 | ICLASS-EN | 38 | 40 | 42 | mA | Class 4 RCLASS = 30.9 Ω ±1% | 9 |
| RCLASS voltage | RCLASS | 1.142 | 1.278 | V | 9 | ||
| Mark, working range | VMARK | 4.9 | 10.1 | V | VPP failing edge | 9 | |
| Mark current | IMARK | 0.25 | 4 | mA | 9 |
CAD (KiCad official)
- Symbol:
PD70101ILQ-TR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
pd70101ilq-tr-etched.step/pd70101ilq-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pd70101ilq-tr.step/pd70101ilq-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (31 pp, sha256
25d7605430c73dad, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).