component
LM5143QRWGRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5143QRWGRQ1
Texas Instruments · DC-DC Converters · VQFN-40-EP(6x6)
LM5143QRWGRQ1 from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SS2 | input | Channel 2 soft-start programming pin; external capacitor and 20-μA current source set error amplifier ramp; pulling below 150 mV disables gate drivers. |
| 2 | COMP2 | output | Channel 2 error amplifier output for external compensation; high impedance in interleave or slave modes. |
| 3 | FB2 | input | Feedback input for 0.6 V regulation; connect to VDDA for 3.3 V or AGND for 5 V fixed output. |
| 4 | CS2 | input | Current sense amplifier input; connect via low-current Kelvin connection to inductor side of sense resistor. |
| 5 | VOUT2 | input | Output voltage sense node; connect to output side of sense resistor for current and voltage feedback. |
| 6 | VCCX | power_in | Optional external bias supply input; internal VCC regulator disabled when greater than 4.3 V; decouple with ceramic capacitor to PGND. |
| 7 | PG2 | output | Open-collector power-good output; goes low when VOUT2 outside 92%-110% regulation window with 25 μs filter delay. |
| 8 | HOL2 | output | Channel 2 high-side gate driver turnoff output; provides active pull-down for high-side MOSFET gate. |
| 9 | HO2 | output | Channel 2 high-side gate driver turnon output; sources up to 3.25 A peak current with 24 ns rise time. |
| 10 | SW2 | passive | Switching node for channel 2 buck converter; connects bootstrap capacitor, high-side MOSFET source, and low-side MOSFET drain. |
| 11 | HB2 | power_out | Bootstrap supply for channel 2 high-side gate driver; requires 0.1 μF ceramic capacitor to SW2. |
| 12 | LOL2 | output | Channel 2 low-side gate driver turnoff output; provides active pull-down for low-side MOSFET gate. |
| 13 | LO2 | output | Channel 2 low-side gate driver turnon output; sources up to 3.25 A peak current with 4 ns rise time. |
| 14 | PGND2 | power_in | Power ground for channel 2 gate driver; connect to system ground plane and output capacitor negative terminal. |
| 15 | VCC | power_out | Regulated 5 V bias supply output for gate drivers; 170 mA minimum sourcing capability; pins 15 and 16 must connect together on PCB. |
| 16 | VCC | power_out | Regulated 5 V bias supply output for gate drivers; 170 mA minimum sourcing capability; pins 15 and 16 must connect together on PCB. |
| 17 | PGND1 | power_in | Power ground for channel 1 gate driver; connect to system ground plane and output capacitor negative terminal. |
| 18 | LO1 | output | Channel 1 low-side gate driver turnon output; sources up to 3.25 A peak current with 4 ns rise time. |
| 19 | LOL1 | output | Channel 1 low-side gate driver turnoff output; provides active pull-down for low-side MOSFET gate. |
| 20 | HB1 | power_out | Bootstrap supply for channel 1 high-side gate driver; requires 0.1 μF ceramic capacitor to SW1. |
| 21 | SW1 | passive | Switching node for channel 1 buck converter; connects bootstrap capacitor, high-side MOSFET source, and low-side MOSFET drain. |
| 22 | HO1 | output | Channel 1 high-side gate driver turnon output; sources up to 3.25 A peak current with 24 ns rise time. |
| 23 | HOL1 | output | Channel 1 high-side gate driver turnoff output; provides active pull-down for high-side MOSFET gate. |
| 24 | PG1 | output | Open-collector power-good output; goes low when VOUT1 outside 92%-110% regulation window with 25 μs filter delay. |
| 25 | VIN | power_in | Primary power supply input for voltage regulators; operates 3.5 V to 65 V steady-state; absolute maximum 70 V. |
| 26 | VOUT1 | input | Output voltage sense node for channel 1; connect to output side of sense resistor for current and voltage feedback. |
| 27 | CS1 | input | Current sense amplifier input for channel 1; connect via low-current Kelvin connection to inductor side of sense resistor. |
| 28 | FB1 | input | Feedback input for 0.6 V regulation; connect to VDDA for 3.3 V or AGND for 5 V fixed output. |
| 29 | COMP1 | output | Channel 1 error amplifier output for external compensation; high impedance in slave mode. |
| 30 | SS1 | input | Channel 1 soft-start programming pin; external capacitor and 20-μA current source set error amplifier ramp; pulling below 150 mV disables gate drivers. |
| 31 | EN1 | input | Active-high enable input for output 1; voltage greater than 2 V enables, less than 0.4 V disables; maximum 70 V; must never float. |
| 32 | RES | output | Hiccup mode restart timer pin; external capacitor sets off-time before auto-restart after 512 consecutive current-limit cycles per channel. |
| 33 | DEMB | input | Diode emulation or synchronization input; low enables DCM, high enables FPWM, or external clock up to 2.5 MHz for synchronization. |
| 34 | MODE | input | Configuration pin for output mode and error amplifier gain; ground for 1200 µS or 10 kΩ to ground for 60 µS ultra-low IQ mode. |
| 35 | AGND | power_in | Analog ground connection; reference return for internal voltage reference and analog signal circuits. |
| 36 | VDDA | power_out | Internal 5 V analog bias regulator output; requires 470 nF ceramic decoupling capacitor to AGND. |
| 37 | RT | input | Oscillator frequency set pin; resistor to AGND determines frequency 100 kHz to 2.2 MHz per equation FSW = 22/(R in kΩ). |
| 38 | DITH | input | Spread spectrum dithering pin; capacitor to AGND charged by 20-μA source modulates frequency ±5%; connect to VDDA to disable. |
| 39 | SYNCOUT | output | Synchronization output; logic-level signal with rising edge 90° lagging HO2 for cascading multiple controllers. |
| 40 | EN2 | input | Active-high enable input for output 2; voltage greater than 2 V enables, less than 0.4 V disables; maximum 70 V; must never float. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Power Management (PMIC) |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
LM5143QRWGRQ1 - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
lm5143qrwgrq1-etched.step/lm5143qrwgrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5143qrwgrq1.step/lm5143qrwgrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (70 pp, sha256
7f505f2c1dac109f, retrieved 2026-09-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).