component
AIP74HC125TA14.TR
Public Made by Adomby adom
Wuxi I core Elec Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAIP74HC125TA14.TR
Wuxi I core Elec · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
AIP74HC125TA14.TR from Wuxi I core Elec, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-LOW output enable input for gate 1; a HIGH level forces output 1Y into the high-impedance OFF-state. |
| 2 | 1A | input | Data input for buffer gate 1; the CMOS level input (HC version) or TTL level input (HCT version) is specified in the features list. |
| 3 | 1Y | tri_state | 3-state data output for gate 1, which goes high-impedance when 1OE is HIGH. |
| 4 | 2OE | input | Active-LOW output enable input for gate 2; a HIGH level forces output 2Y into the high-impedance OFF-state. |
| 5 | 2A | input | Data input for buffer gate 2; input clamp diodes allow current-limited interfacing to voltages above VCC. |
| 6 | 2Y | tri_state | 3-state data output for gate 2, which goes high-impedance when 2OE is HIGH. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages in the datasheet. |
| 8 | 3Y | tri_state | 3-state data output for gate 3, which goes high-impedance when 3OE is HIGH. |
| 9 | 3A | input | Data input for buffer gate 3; input clamp diodes allow current-limited interfacing to voltages above VCC. |
| 10 | 3OE | input | Active-LOW output enable input for gate 3; a HIGH level forces output 3Y into the high-impedance OFF-state. |
| 11 | 4Y | tri_state | 3-state data output for gate 4, which goes high-impedance when 4OE is HIGH. |
| 12 | 4A | input | Data input for buffer gate 4; input clamp diodes allow current-limited interfacing to voltages above VCC. |
| 13 | 4OE | input | Active-LOW output enable input for gate 4; a HIGH level forces output 4Y into the high-impedance OFF-state. |
| 14 | VCC | power_in | Supply voltage; the recommended range for the AiP74HC125 is 2.0 V to 6.0 V (5.0 V typical) with respect to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
AIP74HC125TA14.TR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
aip74hc125ta14-tr-etched.step/aip74hc125ta14-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc125ta14-tr.step/aip74hc125ta14-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (17 pp, sha256
97e55e85e53263e9, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).