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ADM3061EBRZ
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Analog Devices RS-485/RS-422 ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADM3061EBRZ
Analog Devices · RS-485/RS-422 ICs · SOIC-8
ADM3061EBRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver output data is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV, and is tristated when the receiver is disabled (RE driven high). |
| 2 | RE | input | Active-low receiver enable input: driving it low enables the receiver and driving it high disables the receiver. |
| 3 | DE | input | Driver enable input: a high level enables the driver differential outputs A and B, and a low level places the driver output into a high impedance state. |
| 4 | DI | input | Transmit data input: data to be transmitted by the driver is applied to this pin. |
| 5 | GND | power_in | Ground reference pin for the device. |
| 6 | A | bidirectional | Noninverting driver output and receiver input; when the driver is disabled or VCC is powered down, the pin is put into a high impedance state to avoid overloading the bus. |
| 7 | B | bidirectional | Inverting driver output and receiver input; when the driver is disabled or VCC is powered down, the pin is put into a high impedance state to avoid overloading the bus. |
| 8 | VCC | power_in | Power supply rated 3.0 V to 5.5 V; a 0.1 µF decoupling capacitor between VCC and GND is recommended. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| No Load Supply Current (DE = VIO, RE = 0 V) | ICC | 3.5 | 7.5 | mA | DE = VIO1, RE = 0 V | 4 | |
| No Load Supply Current (DE = VIO, RE = VIO) | ICC | 3.5 | 7.5 | mA | DE = VIO, RE = VIO | 4 | |
| No Load Supply Current (DE = 0 V, RE = 0 V) | ICC | 3 | 4.5 | mA | DE = 0 V, RE = 0 V | 4 | |
| Supply Current, Data Rate = 500 kbps (VCC ≥ 4.5 V) | ICC | 100 | 165 | mA | RL = 54 Ω, DE = VIO, RE = 0 V (VCC ≥ 4.5 V) | 4 | |
| Supply Current, Data Rate = 500 kbps (VCC = 3.0 V) | ICC | 56 | 74 | mA | RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V) | 4 | |
| Supply Current in Shutdown Mode | ISHDN | 210 | 450 | µA | DE = 0 V, RE = VIO | 4 | |
| Output Voltage, Loaded (VCC ≥ 3.0 V, RL = 50 Ω) | /VOD2/ | 2 | 2.5 | V | VCC ≥ 3.0 V, RL = 50 Ω, see Figure 38 | 4 | |
| Output Voltage, Loaded (VCC ≥ 3.0 V, RS-485 RL = 27 Ω) | /VOD2/ | 1.5 | 2.1 | V | VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 38 | 4 | |
| Output Voltage, Loaded (VCC ≥ 4.5 V, RL = 50 Ω) | /VOD2/ | 2.1 | 3.5 | V | VCC ≥ 4.5 V, RL = 50 Ω, see Figure 38 | 4 | |
| Output Voltage, Loaded (VCC ≥ 4.5 V, RS-485 RL = 27 Ω) | /VOD2/ | 2.1 | 3 | V | VCC ≥ 4.5 V, RL = 27 Ω (RS-485), see Figure 38 | 4 | |
| Output Voltage over Common-Mode Range (VCC ≥ 3.0 V) | /VOD3/ | 1.5 | 2.1 | V | VCC ≥ 3.0 V, −7 V ≤ VCM ≤ +12 V, see Figure 39 | 4 | |
| Output Voltage over Common-Mode Range (VCC ≥ 4.5 V) | /VOD3/ | 2.1 | 3 | V | VCC ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 39 | 4 | |
| Change in Magnitude of Differential Output Voltage | ∆/VOD/ | 0.2 | V | RL = 27 Ω or 50 Ω, see Figure 38 | 4 | ||
| Common-Mode Output Voltage | VOC | 1.6 | 3 | V | RL = 27 Ω or 50 Ω, see Figure 38 | 4 | |
| Change in Common-Mode Voltage (Complementary Output States) | ∆/VOC/ | 0.2 | V | RL = 27 Ω or 50 Ω, see Figure 38 | 4 | ||
| Output Short-Circuit Current | IOS | -250 | 250 | mA | −7 V < output voltage (VOUT) < +12 V | 4 | |
| Output Leakage (Y, Z), high | IO | 100 | µA | DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, input voltage (VIN) = 12 V | 4 | ||
| Output Leakage (Y, Z), low | IO | -100 | µA | DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V | 4 | ||
| Input Current (logic inputs DE, RE, DI) | II | -2 | 2 | µA | DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO | 4 | |
| Differential Input Threshold Voltage | VTH | -200 | -125 | -30 | mV | −7 V < VCM < +12 V | 4 |
| Input Current (A, B) at VIN = 12 V | II | 0.1 | 0.25 | mA | DE = 0 V, VCC = powered/unpowered, VIN = 12 V | 4 | |
| Input Current (A, B) at VIN = −7 V | II | -0.2 | -0.1 | mA | DE = 0 V, VCC = powered/unpowered, VIN = −7 V | 4 | |
| Line Input Resistance | RIN | 48 | 96 | kΩ | −7 V ≤ VCM ≤ +12 V | 4 | |
| VCC to GND | 6 | V | 8 | ||||
| Digital Input and Output Voltage (DE, RE, DI, and RO), lower limit | -0.3 | V | Referenced to VIO + 0.3 V upper limit (VIO = VCC on ADM3061E) | 8 | |||
| Driver Output and Receiver Input Voltage | -9 | 14 | V | 8 | |||
| Operating Temperature Range (B grade) | -40 | 125 | °C | B grade | 8 | ||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Continuous Total Power Dissipation (8-Lead SOIC_N) | 0.225 | W | 8-Lead SOIC_N | 8 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 8 | |||
| Lead Temperature, Soldering | 300 | °C | 10 sec | 8 | |||
| Lead Temperature, Vapor Phase | 215 | °C | 60 sec | 8 | |||
| Lead Temperature, Infrared | 220 | °C | 15 sec | 8 | |||
| ESD IEC 61000-4-2 Contact Discharge (bus pins) | -12 | 12 | kV | Bus pins (A, B, Y, Z) | 8 | ||
| ESD IEC 61000-4-2 Air Discharge (bus pins) | -12 | 12 | kV | 10 Positive and 10 Negative Discharges | 8 | ||
| ESD IEC 61000-4-2 Air Discharge (bus pins) | -15 | 15 | kV | Three Positive or Three Negative Discharges | 8 | ||
| ESD Human Body Model (bus pins) | -30 | 30 | kV | On the Bus Pins (A, B, Y, Z) | 8 | ||
| ESD Human Body Model (all other pins) | -8 | 8 | kV | All Other Pins | 8 | ||
| Thermal Resistance Junction-to-Ambient (R-8, SOIC_N) | θJA | 110.88 | °C/W | Package R-8; JEDEC 2S2P thermal test board with no bias | 8 | ||
| Thermal Resistance Junction-to-Case (R-8, SOIC_N) | θJC | 58.63 | °C/W | Package R-8; JEDEC 2S2P thermal test board with no bias | 8 | ||
| Supply Voltage VCC | VCC | 3 | 5.5 | V | Operating range as stated in Specifications header (VCC = 3.0 V to 5.5 V) | 4 |
CAD (KiCad official)
- Symbol:
ADM3061EBRZ - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
adm3061ebrz-etched.step/adm3061ebrz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adm3061ebrz.step/adm3061ebrz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (25 pp, sha256
7ce4130f0f613a46, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).