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ADS802U

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Texas Instruments Analog To Digital Converters (ADC), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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ADS802U

Texas Instruments · Analog To Digital Converters (ADC) · SOIC-28-300mil

ADS802U from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane.
2 B1 tri_state Bit 1, the most significant bit (MSB) of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
3 B2 tri_state Bit 2 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
4 B3 tri_state Bit 3 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
5 B4 tri_state Bit 4 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
6 B5 tri_state Bit 5 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
7 B6 tri_state Bit 6 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
8 B7 tri_state Bit 7 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
9 B8 tri_state Bit 8 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
10 B9 tri_state Bit 9 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
11 B10 tri_state Bit 10 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
12 B11 tri_state Bit 11 of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
13 B12 tri_state Bit 12, the least significant bit (LSB) of the 12-bit output data, CMOS logic output with logic LOW 0 to 0.4 V and logic HIGH 2.0 V to +VS, placed in high impedance when OE is HIGH.
14 GND power_in Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane.
15 +VS power_in +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible.
16 CLK input Convert clock input accepting a CMOS-level clock; duty cycle should be held at 50% with rise and fall times of 2 ns or less.
17 +VS power_in +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible.
18 OE input Output enable: HIGH puts the digital outputs into a high-impedance state (intended for testability, not for driving buses directly); LOW or floating gives normal operation through an internal pull-down resistor.
19 MSBI input Most significant bit inversion: HIGH inverts the MSB for Binary Two's Complement output; LOW or floating gives Straight Offset Binary output through an internal pull-down resistor.
20 +VS power_in +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible.
21 REFB passive Bottom reference bypass for the internal +1.25 V reference; an externally applied bottom reference must be no less than +1.1 V.
22 CM passive Common-mode voltage, derived as (REFT + REFB)/2 (+2.25 V nominal); keep the current drawn from this pin below 0.5 µA to avoid nonlinearity in the internal reference ladder.
23 REFT passive Top reference bypass for the internal +3.25 V reference; an externally applied top reference must be no more than +3.4 V.
24 +VS power_in +5V power supply; operating range +4.75 V to +5.25 V (typical +5.0 V), with power supplies bypassed by 0.1 µF ceramic capacitors as close to the pin as possible.
25 GND power_in Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane.
26 IN input Non-inverted analog input; each differential input spans +1.25 V to +3.25 V, centered on the +2.25 V common-mode voltage, and should be bypassed with 22 pF capacitors to minimize track-and-hold glitches.
27 IN input Complementary analog input (180° out of phase with IN); each differential input spans +1.25 V to +3.25 V, centered on the +2.25 V common-mode voltage, and should be bypassed with 22 pF capacitors to minimize track-and-hold glitches.
28 GND power_in Ground pin; the analog and digital ground pins should be connected directly to the analog ground plane.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-28-300mil
Category Data Acquisition
Pins 28

CAD (KiCad official)

  • Symbol: ADS802U
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: ads802u-etched.step / ads802u-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads802u.step / ads802u.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 cf2e9fff9145f16b, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF