NCD57080BDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Input-side power supply; a good quality bypass capacitor is required from this pin to GND1, placed close to the pins, and the UVLO circuit enables operation at power-on when a typical supply above VUVLO1-OUT-ON is present.
2	IN+	input	Non-inverting gate driver input, internally clamped to GND1 with an equivalent 125 kΩ pull-down to keep the output low without an input signal, and a minimum positive or negative pulse width is required before OUT responds.
3	IN−	input	Inverting gate driver input, internally clamped to VDD1 with an equivalent 125 kΩ pull-up to keep the output low without an input signal, and a minimum positive or negative pulse width is required before OUT responds.
4	GND1	power_in	Input-side ground reference.
5	VDD2	power_in	Output-side positive power supply whose operating range runs from UVLO2 to its maximum allowed value; a good quality bypass capacitor is required from this pin to GND2, placed close to the pins.
6	OUT	output	Driver output that provides the drive voltage and source/sink current to the IGBT/MOSFET gate, rated for 6.5 A peak sourcing and 6.5 A peak sinking (pulsed), and is actively pulled low during start-up.
7	GND2	power_in	Output-side gate drive reference connected to the IGBT emitter or MOSFET source (pin 7 on version B; pin 8 on versions A and C).
8	VEE2	power_in	Output-side negative power supply with a good quality bypass capacitor required from this pin to GND2 placed close to the pin; VEE2-GND2 is rated from -18 V to 0.3 V.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	SOIC-8
Category	Power Management ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage, Input Side (VDD1-GND1)	VDD1−GND1	-0.3		22	V		6
Positive Power Supply, Output Side (VDD2-GND2)	VDD2−GND2	-0.3		32	V		6
Negative Power Supply, Output Side (VEE2-GND2)	VEE2−GND2	-18		0.3	V		6
Differential Power Supply, Output Side (VMAX2), NCx5708zB	VDD2−VEE2 (VMAX2)	0		36	V	NCx5708zB	6
Gate-driver Output Low Voltage, NCx5708zA/B	VOUT−GND2	-0.3			V	NCx5708zA/B	6
Voltage at IN+, IN−	VLIM−GND1	-0.3			V		6
Gate-driver Output Sourcing Current	IPK−SRC			6.5	A	maximum pulse width = 10 µs, maximum duty cycle = 0.2%, VDD2 = 15 V, VEE2 = 0 V	6
Gate-driver Output Sinking Current	IPK−SNK			6.5	A	maximum pulse width = 10 µs, maximum duty cycle = 0.2%, VDD2 = 15 V, VEE2 = 0 V	6
Power Dissipation (SOIC-8 Narrow Package)	PD			1315	mW		6
Maximum Junction Temperature	TJ(max)	-40		150	°C		7
Storage Temperature Range	TSTG	-65		150	°C		7
ESD Capability, Human Body Model	ESDHBM	-2		2	kV	AEC-Q100-002 (EIA/JESD22-A114)	7
Supply Voltage, Input Side (operating range)	VDD1−GND1			20	V		7
Positive Power Supply, Output Side (operating range)	VDD2−GND2			30	V		7
Negative Power Supply, Output Side (operating range), NCx5708zB	VEE2−GND2	-15		0	V	NCx5708zB	7
Differential Power Supply, Output Side (VMAX2) operating range, NCx5708zB	VDD2−VEE2 (VMAX2)	0		32	V	NCx5708zB	7
Low Level Input Voltage at IN+, IN−	VIL	0			V		7
Common Mode Transient Immunity	/dVISO/dt/	100			kV/s	Note 8: tested by ±1500 V pulses up to 100 kV/s	7
Ambient Temperature	TA	-40		125	°C		7
UVLO1 Output Enabled	VUVLO1−OUT−ON			3.1	V	UVLO1 Output Enabled	8
UVLO1 Output Disabled	VUVLO1−OUT−OFF	2.4			V	UVLO1 Output Disabled	8
UVLO1 Hysteresis	VUVLO1−HYST	0.1			V		8
UVLO2 Output Enabled, NCx57080y	VUVLO2−OUT−ON	12.4	12.9	13.4	V	NCx57080y	8
UVLO2 Output Disabled, NCx57080y	VUVLO2−OUT−OFF	11.5	12	12.5	V	NCx57080y	8
UVLO2 Hysteresis	VUVLO2−HYST	0.7	1		V		8
Input Supply Quiescent Current (VDD1 = 3.3 V)	IDD1−0−3.3			2	mA	IN+ = Low, IN− = Low, VDD1 = 3.3 V	8
Input Supply Quiescent Current (VDD1 = 5 V)	IDD1−0−5			2	mA	IN+ = Low, IN− = Low	8
Input Supply Quiescent Current (VDD1 = 15 V)	IDD1−0−15			2	mA	IN+ = Low, IN− = Low, VDD1 = 15 V	8
Input Supply Current, IN+ High	IDD1−100−5			5.5	mA	IN+ = High, IN− = Low	8
Output Positive Supply Quiescent Current	IDD2−0			2	mA	IN+ = Low, IN− = Low, no load	8
Output Positive Supply Current, IN+ High	IDD2−100			2	mA	IN+ = High, IN− = Low, no load	8
Output Negative Supply Quiescent Current (NCx5708zB)	IEE2−0			2	mA	IN+ = Low, IN− = Low, no load, VEE2 = −8 V	8
Output Negative Supply Current, IN+ High (NCx5708zB)	IEE2−100			2	mA	IN+ = High, IN− = Low, no load, VEE2 = −8 V	8
IN− Input Current (VDD1 = 3.3 V)	IIN−L−3.3			100	µA	VIN− = 0 V, VDD1 = 3.3 V	8
IN− Input Current (VDD1 = 5 V)	IIN−L−5			100	µA	VIN− = 0 V	8
IN− Input Current (VDD1 = 15 V)	IIN−L−15			100	µA	VIN− = 0 V, VDD1 = 15 V	8
IN− Input Current (VDD1 = 20 V)	IIN−L−20			100	µA	VIN− = 0 V, VDD1 = 20 V	8
IN+ Input Current (VDD1 = 3.3 V)	IIN+H−3.3			100	µA	VIN+ = VDD1 = 3.3 V	8
IN+ Input Current (VDD1 = 5 V)	IIN+H−5			100	µA	VIN+ = VDD1 = 5 V	8
IN+ Input Current (VDD1 = 15 V)	IIN+H−15			100	µA	VIN+ = VDD1 = 15 V	8
IN+ Input Current (VDD1 = 20 V)	IIN+H−20			100	µA	VIN+ = VDD1 = 20 V	8
Input Pulse Width for Guaranteed No Response at Output	tON−MIN1			10	ns		8
Input Pulse Width for Guaranteed Response at Output	tON−MIN2	40			ns		8
Output Low State	VOUTL1		0.15	0.3	V	ISINK = 200 mA	9
Output Low State (high sink current)	VOUTL2			0.8	V	ISINK = 1.0 A, TA = 25°C (Note 12)	9
Output High State	VOUTH1		0.2	0.35	V	ISRC = 200 mA	9
Output High State (high source current)	VOUTH2			1	V	ISRC = 1.0 A, TA = 25°C (Note 12)	9
Clamping Voltage, Sourcing (VOUT / VOUTH − VDD2)	VCLAMP−OUTH		0.7	1.3	V	IN+ = Low, IN− = High, ICLAMP−OUT/OUTH = 500 mA, (pulse test, tCLPmax = 10 µs)	9
Clamping Voltage, Sinking (VOUTL − VDD2)	VCLAMP−OUTL		0.8	1.5	V	IN+ = High, IN− = Low, ICLAMP−OUTL = 500 mA, (pulse test, tCLPmax = 10 µs)	9
Propagation Delay IN+, IN− to Output High (3.3 V)	tPD−ON−3.3	40	60	90	ns	VDD1 = VIN+ = 3.3V, VIN− = 0 V	9
Propagation Delay IN+, IN− to Output High (5 V)	tPD−ON−5	40	60	90	ns	VDD1 = VIN+ = 5 V, VIN− = 0 V	9
Propagation Delay IN+, IN− to Output High (15 V)	tPD−ON−15	40	60	90	ns	VDD1 = VIN+ = 15 V, VIN− = 0 V	9
Propagation Delay IN+, IN− to Output High (20 V)	tPD−ON−20	40	60	90	ns	VDD1 = VIN+ = 20 V, VIN− = 0 V	9
Propagation Delay IN+, IN− to Output Low (3.3 V)	tPD−OFF−3.3	40	60	90	ns	VDD1 = VIN+ = 3.3 V, VIN− = 0 V	9
Propagation Delay IN+, IN− to Output Low (5 V)	tPD−OFF−5	40	60	90	ns	VDD1 = VIN+ = 5 V, VIN− = 0 V	9
Propagation Delay IN+, IN− to Output Low (15 V)	tPD−OFF−15	40	60	90	ns	VDD1 = VIN+ = 15 V, VIN− = 0 V	9
Propagation Delay IN+, IN− to Output Low (20 V)	tPD−OFF−20	40	60	90	ns	VDD1 = VIN+ = 20 V, VIN− = 0 V	9
Propagation Delay Distortion (TA = −40 °C to 125 °C)	tDISTORT	-25		25	ns	TA = −40°C to 125°C, PW > 150 ns	9
Prop Delay Distortion between Parts	tDISTORT_TOT	-30	0	30	ns	PW > 150 ns	9
Thermal Resistance, Junction-to-Air, SOIC-8 narrow body	RJA		95		°C/W	4-Layer (Note 5: 100 mm² copper, 1 oz, FR4 PCB)	7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	ABS		RIO Insulation Resistance at TS, VIO = 500 V 109 Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1)	6

CAD (KiCad official)

Symbol: NCD57080BDR2G
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ncd57080bdr2g-etched.step / ncd57080bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncd57080bdr2g.step / ncd57080bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (24 pp, sha256 748b3eca1fc6dfa7, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

NCD57080BDR2G

Verified NCD57080BDR2G

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README