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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

HMC704LP4ETR

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · QFN-24-EP(4x4)

HMC704LP4ETR from Analog Devices, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDI	input	Main Serial port data input for SPI communication.
2	SCK	input	Main Serial port clock input for SPI communication.
3	ASEN	output	Auxiliary Serial Port Enable Output.
4	LD_SDO	output	Lock Detect Output or Serial Data Output or General Purpose Output, selectable via Reg 0Fh.
5	VCOIN	input	Complementary input to RF Prescaler, internally biased to 2.0V DC, requires 100pF ceramic bypass capacitor to ground plane for single-ended operation.
6	VCOIP	input	Input to RF Prescaler from external VCO, small signal with internal 2.0V DC bias, requires external AC coupling.
7	VCCHF	power_in	Power supply pin for RF Section, nominal +3.3V, requires decoupling capacitor placed as close as possible to pin.
8	N/C	unconnected	No Connect pad.
9	VCCPS	power_in	Power supply for RF Prescaler, nominal +3.3V.
10	N/C	unconnected	No Connect pad.
11	VCCPD	power_in	Power supply for phase detector, nominal +3.3V.
12	BIAS	power_out	Precision bias reference voltage output, 1.920V ±20mV nominal, requires external bypass decoupling, cannot drive external loads, must be measured with ≥10GΩ meter.
13	N/C	unconnected	No Connect pad.
14	AVDD	power_in	Power supply for analog bias generation circuits, nominal +3.3V.
15	VPPCP	power_in	Power supply for charge pump, nominal +5V, must be equal to VDDLS.
16	CP	output	Charge pump output for external loop filter VCO tuning control.
17	VDDLS	power_in	Power supply for charge pump digital section, nominal +5V, must be equal to VPPCP.
18	RVDD	power_in	Power supply for reference path, nominal +3.3V.
19	XREFP	input	Reference input for external crystal oscillator, supports DC to 350MHz with 100Ω
20	ASCK	output	Auxiliary Serial Port Clock Output for external slave devices.
21	ASD	output	Auxiliary Serial Port Data Output for external slave devices.
22	DVDD	power_in	Digital power supply, nominal +3.3V.
23	CEN	input	Hardware Chip Enable input, active low controls chip enable/power down mode per Reg 01h[0].
24	SEN	input	Main Serial port latch enable input for SPI control, active low.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	QFN-24-EP(4x4)
Category	Clock/Timing
Pins	25

CAD (KiCad official)

Symbol: HMC704LP4ETR
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: hmc704lp4etr-etched.step / hmc704lp4etr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hmc704lp4etr.step / hmc704lp4etr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (44 pp, sha256 75728b3e1eed87df, retrieved 2026-09-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF