component
74HC244DRG
Public Made by Adomby adom
HANSCHIP semiconductor Buffers, Drivers, Receivers, Transceivers, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdown74HC244DRG
HANSCHIP semiconductor · Buffers, Drivers, Receivers, Transceivers · SOP-20
74HC244DRG from HANSCHIP semiconductor, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Active-LOW output enable for outputs 1Y0 to 1Y3; a HIGH on this input forces those outputs into the high-impedance OFF-state. |
| 2 | 1A0 | input | Data input for the first buffer of the 1OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 3 | 2Y0 | tri_state | Non-inverting 3-state bus output of the 2OE group, high-impedance when 2OE is HIGH. |
| 4 | 1A1 | input | Data input for the second buffer of the 1OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 5 | 2Y1 | tri_state | Non-inverting 3-state bus output of the 2OE group, high-impedance when 2OE is HIGH. |
| 6 | 1A2 | input | Data input for the third buffer of the 1OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 7 | 2Y2 | tri_state | Non-inverting 3-state bus output of the 2OE group, high-impedance when 2OE is HIGH. |
| 8 | 1A3 | input | Data input for the fourth buffer of the 1OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 9 | 2Y3 | tri_state | Non-inverting 3-state bus output of the 2OE group, high-impedance when 2OE is HIGH. |
| 10 | GND | power_in | Ground reference (0 V). |
| 11 | 2A3 | input | Data input for the fourth buffer of the 2OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 12 | 1Y3 | tri_state | Non-inverting 3-state bus output of the 1OE group, high-impedance when 1OE is HIGH. |
| 13 | 2A2 | input | Data input for the third buffer of the 2OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 14 | 1Y2 | tri_state | Non-inverting 3-state bus output of the 1OE group, high-impedance when 1OE is HIGH. |
| 15 | 2A1 | input | Data input for the second buffer of the 2OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 16 | 1Y1 | tri_state | Non-inverting 3-state bus output of the 1OE group, high-impedance when 1OE is HIGH. |
| 17 | 2A0 | input | Data input for the first buffer of the 2OE group, with clamp diodes that allow current-limiting resistors for interfacing to voltages above VCC. |
| 18 | 1Y0 | tri_state | Non-inverting 3-state bus output of the 1OE group, high-impedance when 1OE is HIGH. |
| 19 | 2OE | input | Active-LOW output enable for outputs 2Y0 to 2Y3; a HIGH on this input forces those outputs into the high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V for 74HC244 and 4.5 V to 5.5 V for 74HCT244 per recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 4 | |
| output current | IO | -35 | 35 | mA | -0.5V < VO < VCC+0.5V | 4 | |
| supply current | ICC | 70 | mA | 4 | |||
| ground current | IGND | -70 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | ℃ | 4 | ||
| total power dissipation | Ptot | 500 | mW | 4 | |||
| soldering temperature | TL | 245 | ℃ | 10s | 4 | ||
| supply voltage (74HC244) | VCC | 2 | 5 | 6 | V | 4 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 4 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 4 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 4 | ||
| ambient temperature | Tamb | -40 | 85 | ℃ | 4 | ||
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V | 5 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V | 5 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V | 5 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V | 5 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO=-20uA; VCC=4.5V | 5 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO=-20uA; VCC=6.0V | 5 | |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; IO=-6.0mA; VCC=4.5V | 5 | |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | VI = VIH or VIL; IO=-7.8mA; VCC=6.0V | 5 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO=20uA; VCC=4.5V | 5 | |
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | VI = VIH or VIL; IO=6.0mA; VCC=4.5V | 5 | |
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; IO=7.8mA; VCC=6.0V | 5 | |
| input leakage current | II | -0.1 | 0.1 | uA | VI=VCC or GND; VCC=6.0V | 5 | |
| OFF-state output current | IOZ | -0.5 | 0.5 | uA | VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 5 | |
| supply current | ICC | 8 | uA | VI=VCC or GND; IO=0A; VCC=6.0V | 5 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC=4.5V | 6 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC=6.0V | 6 | ||
| LOW-level input voltage | VIL | 1.35 | V | VCC=4.5V | 6 | ||
| LOW-level input voltage | VIL | 1.8 | V | VCC=6.0V | 6 | ||
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; IO=-20uA; VCC=4.5V | 6 | ||
| HIGH-level output voltage | VOH | 5.9 | V | VI = VIH or VIL; IO=-20uA; VCC=6.0V | 6 | ||
| HIGH-level output voltage | VOH | 3.84 | V | VI = VIH or VIL; IO=-6.0mA; VCC=4.5V | 6 | ||
| HIGH-level output voltage | VOH | 5.34 | V | VI = VIH or VIL; IO=-7.8mA; VCC=6.0V | 6 | ||
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO=20uA; VCC=4.5V | 6 | ||
| LOW-level output voltage | VOL | 0.33 | V | VI = VIH or VIL; IO=6.0mA; VCC=4.5V | 6 | ||
| input leakage current | II | -1 | 1 | uA | VI=VCC or GND; VCC=6.0V | 6 | |
| OFF-state output current | IOZ | -5 | 5 | uA | VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 6 | |
| supply current | ICC | 80 | uA | VI=VCC or GND; IO=0A; VCC=6.0V | 6 | ||
| propagation delay nAn to nYn | tpd | 11 | 22 | ns | VCC=4.5V; see Figure 5 | 7 | |
| propagation delay nAn to nYn | tpd | 9 | 19 | ns | VCC=6.0V; see Figure 5 | 7 | |
| enable time nOE to nYn | ten | 13 | 30 | ns | VCC=4.5V; see Figure 6 | 7 | |
| enable time nOE to nYn | ten | 10 | 26 | ns | VCC=6.0V; see Figure 6 | 7 | |
| disable time nOE to nYn | tdis | 14 | 30 | ns | VCC=4.5V; see Figure 6 | 7 | |
| disable time nOE to nYn | tdis | 11 | 26 | ns | VCC=6.0V; see Figure 6 | 7 | |
| transition time | tt | 5 | 12 | ns | VCC=4.5V; see Figure 5 | 7 | |
| transition time | tt | 4 | 10 | ns | VCC=6.0V; see Figure 5 | 7 | |
| propagation delay nAn to nYn | tpd | 28 | ns | VCC=4.5V; see Figure 5 | 8 | ||
| propagation delay nAn to nYn | tpd | 24 | ns | VCC=6.0V; see Figure 5 | 8 | ||
| enable time nOE to nYn | ten | 38 | ns | VCC=4.5V; see Figure 6 | 8 | ||
| enable time nOE to nYn | ten | 33 | ns | VCC=6.0V; see Figure 6 | 8 | ||
| disable time nOE to nYn | tdis | 38 | ns | VCC=4.5V; see Figure 6 | 8 | ||
| disable time nOE to nYn | tdis | 33 | ns | VCC=6.0V; see Figure 6 | 8 | ||
| transition time | tt | 15 | ns | VCC=4.5V; see Figure 5 | 8 | ||
| transition time | tt | 13 | ns | VCC=6.0V; see Figure 5 | 8 |
CAD (KiCad official)
- Symbol:
74HC244DRG - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74hc244drg-etched.step/74hc244drg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc244drg.step/74hc244drg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HANSCHIP semiconductor datasheet (14 pp, sha256
89ae331fa36a036e, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).