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TPS610333DRLR

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Texas Instruments DC-DC Converters, SOT-583-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps610333drlrfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TPS610333DRLR

Texas Instruments · DC-DC Converters · SOT-583-8

TPS610333DRLR from Texas Instruments, in a SOT-583-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in IC power supply input for the converter.
2 EN input Enable logic input: a logic-high voltage enables the device, and a logic-low voltage disables it and puts it into shutdown mode.
3 MODE input Light-load operation mode select: tied to logic high selects forced PWM mode, and tied to logic low selects auto PFM mode.
4 PG output Power good indicator, an open-drain output.
5 FB input For TPS610333 this pin should be connected to VIN to set a fixed 5.0 V output voltage.
6 GND power_in Ground pin of the IC.
7 SW passive Switch pin of the converter, connected to the drain of the internal low-side power MOSFET and the source of the internal high-side power MOSFET.
8 VOUT power_out Boost converter output.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-583-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage range at terminals VIN, EN, FB, SW, VOUT -0.3 7 V Voltage range at terminals VIN, EN, FB, SW, VOUT (w.r.t. network ground) 5
SW spike voltage -0.7 8 V SW spike at 10ns 5
SW spike voltage -0.7 9 V SW spike at 1ns 5
Operating junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Input voltage range VIN 1.8 5.5 V 5
Output voltage setting range VOUT 2.2 5.5 V 5
Effective inductance range L 0.33 0.47 1.3 µH 5
Effective input capacitance range CIN 1 4.7 µF 5
Effective output capacitance range COUT 4 10 1000 µF IOUT <= 1A 5
Effective output capacitance range COUT 10 20 1000 µF IOUT > 1A 5
Operating junction temperature TJ -40 125 °C 5
Quiescent current into VIN pin IQ 13 20 25 µA IC enabled, No load, No switching, VIN = 1.8 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C 6
Quiescent current into VOUT pin IQ 5.3 9 µA IC enabled, No load, No switching, VOUT = 2.2 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C 6
Shutdown current into VIN and SW pin ISD 0.1 0.2 µA IC disabled, VIN = VSW = 3.6 V, TJ = 25°C 6
Fixed output voltage VOUT (fixed 5V) 4.93 5 5.07 V FB connected to VIN, VIN < VOUT, PWM mode 6
Reference voltage at the FB pin VREF 591 600 609 mV PWM mode 6
Output over-voltage protection threshold VOVP 5.5 5.75 6 V VOUT rising 6
Leakage current at FB pin IFB_LKG 4 25 nA TJ = 25°C 6
Leakage current at FB pin IFB_LKG 5 30 nA TJ = 125°C 6
Leakage current into VOUT pin IVOUT_LKG 0.2 0.5 µA IC disabled, VIN = 0 V, VSW = 0 V, VOUT = 5.5 V, TJ = 25°C 6
Switching frequency fSW 2 2.4 2.8 MHz VIN = 3.6 V, VOUT = 5.0 V, PWM mode 6
Minimum on time tON_min 20 48 65 ns 6
Minimum off time tOFF_min 35 70 ns 6
Valley current limit (TPS610333) ILIM_SW 1.55 1.85 2.25 A VIN = 3.6 V, VOUT = 5.0 V 6
Maximum pre-charge current (TPS610333) ILIM_CHG_max 800 1100 mA VIN = 2.4 V, VOUT > 0.4 V 6
Power good upper threshold PGDOV 105 107 110 % % of VOUT setting 6
Power good lower threshold PGDUV 91 93 95 % % of VOUT setting 6
Under-voltage lockout threshold VIN_UVLO 1.7 1.79 V VIN rising 6
Under-voltage lockout threshold VIN_UVLO 1.6 V VIN falling 6
VIN UVLO hysteresis VIN_HYS 65 mV 6
Reference voltage at the FB pin VREF 606 mV PFM mode 6
Output over-voltage protection hysteresis VOVP_HYS 0.11 V 6
Soft startup time tss 0.86 ms Internal SS ramp time 6
High-side MOSFET on resistance RDS(on) 46 mΩ VOUT = 5.0 V 6
Low-side MOSFET on resistance RDS(on) 25 mΩ VOUT = 5.0 V 6
Reverse current limit (MODE=1) IREVERSE -1.4 A VIN = 3.6 V, VOUT = 5.0 V; MODE = 1 6
Pre-charge current ILIM_CHG 330 mA VIN = 1.8 - 5.5 V, VOUT < 0.4 V 6
EN logic high threshold VEN_H 1.2 V VIN > 1.8 V or VOUT > 2.2 V 6
EN logic low threshold VEN_L 0.4 V VIN > 1.8 V or VOUT > 2.2 V 6
MODE Logic high threshold VMODE_H 1.2 V VIN > 1.8 V or VOUT > 2.2 V 6
MODE Logic Low threshold VMODE_L 0.4 V VIN > 1.8 V or VOUT > 2.2 V 6
EN pins internal pull-down resistor RDOWN 10 MΩ EN pins 6
MODE pins internal pull-down resistor RDOWN 1 MΩ MODE pins 6
PGOOD upper threshold hysteresis (rising & falling) PGDHYST 2.5 % % of VOUT setting 6
Delay time to PGOOD high signal tPGDFLT(rise) 1.3 ms 6
Glitch filter time of PGOOD tPGDFLT(fall) 33 µs 6
Thermal shutdown threshold TSD 170 °C TJ rising 6
Thermal shutdown threshold TSD 155 °C TJ falling 7
Thermal shutdown hysteresis TSD_HYS 15 °C TJ falling below TSD 7
Junction-to-ambient thermal resistance RθJA 117.5 °C/W First thermal column (standard board, no EVM footnote) 5
Junction-to-ambient thermal resistance RθJA 65.8 °C/W Measured on TPS61033EVM, 4-layer, 2oz copper NA PCB 5
Junction-to-case thermal resistance RθJC 40 °C/W First thermal column 5
Junction-to-board thermal resistance RθJB 23 °C/W First thermal column 5
Junction-to-top characterization parameter ΨJT 2.8 °C/W First thermal column 5
Junction-to-top characterization parameter ΨJT 1 °C/W Measured on TPS61033EVM, 4-layer, 2oz copper NA PCB 5
Junction-to-board characterization parameter ΨJB 22.9 °C/W First thermal column 5
Junction-to-board characterization parameter ΨJB 28.4 °C/W Measured on TPS61033EVM, 4-layer, 2oz copper NA PCB 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper For better thermal performance, TI suggest to make copper polygon connected with each pin bigger. 20

CAD (KiCad official)

  • Symbol: TPS610333DRLR
  • Footprint: Package_TO_SOT_SMD:SOT-583-8
  • 3D model: SOT-583-8 (KiCad packages3D, STEP)
  • 3D model files: tps610333drlr-etched.step / tps610333drlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps610333drlr.step / tps610333drlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 ad649d9686d7262b, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF