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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

ACPL-061L-500E

Broadcom AVAGO · Logic Output Optoisolators · SOIC-8

ACPL-061L-500E from Broadcom AVAGO, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	Not connected on the ACPL-061L SO-8 package.
2	Anode	input	LED anode input; the datasheet specifies an input forward current of 1.6 mA to 6.0 mA (IFH) with a 8 mA maximum average forward input current.
3	Cathode	input	LED cathode input; the datasheet specifies a maximum average forward input current of 8 mA and a reverse input voltage of 5 V maximum.
4	NC	unconnected	Not connected on the ACPL-061L SO-8 package.
5	GND	power_in	Output-side ground; a 0.1 µF bypass capacitor must be connected between VDD and GND, with total lead length not exceeding 20 mm.
6	Vo	output	Push-pull CMOS output with slew-rate control; output voltage is limited to -0.5 V to VDD + 0.5 V and output current to 10 mA maximum.
7	NC	unconnected	Not connected on the ACPL-061L (footnote states pin 7 is not connected).
8	VDD	power_in	Output-side supply; the recommended supply range is 2.7 V to 5.5 V with a 6.5 V absolute maximum, and a 0.1 µF bypass capacitor is required between VDD and GND.

Key specifications

Parameter	Value
Manufacturer	Broadcom AVAGO
Package	SOIC-8
Category	Optoisolators
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage Temperature	TS	-55		125	°C		6
Operating Temperature	TA	-40		105	°C		6
Reverse Input Voltage	VR			5	V		6
Supply Voltage	VDD			6.5	V		6
Average Forward Input Current	IF			8	mA		6
Peak Forward Input Current	IF(TRAN)			1	A	≤1 s Pulse Width, <300 pulses per second	6
Peak Forward Input Current	IF(TRAN)			80	mA	≤1 s Pulse Width, <10% Duty Cycle	6
Output Current	IO			10	mA		6
Output Voltage	VO	-0.5			V		6
Input Power Dissipation	PI			14	mW		6
Output Power Dissipation	PO			20	mW		6
Lead Solder Temperature	TLS			260	°C	for 10 sec., 1.6 mm below seating plane	6
Operating Temperature	TA	-40		105	°C		7
Input Current, Low Level	IFL	0		250	A		7
Input Current, High Level	IFH	1.6		6	mA		7
Power Supply Voltage	VDD	2.7		5.5	V		7
Forward Input Voltage	VF(OFF)			0.8	V		7
Logic Low Input Voltage	VIL	0		0.8	V		7
Input Forward Voltage	VF	0.95	1.3	1.7	V	IF = 2 mA	7
Input Reverse Breakdown Voltage	BVR	3	5		V	VIR = 10 A	7
Logic Low Output Voltage	VOL		0.03	0.1	V	IF = 2 mA, VI = 5 V (RT = 1.68 k) or VI = 3.3V (RT = 870), IO = 20 A	7
Logic Low Output Voltage	VOL		0.18	0.4	V	IF = 2 mA, VI = 5 V (RT = 1.68 k) or VI = 3.3V (RT = 870), IO = 3.2 mA	7
Input Threshold Current	ITH		0.7	1.3	mA		7
Logic Low Output Supply Current	IDDL		0.8	1.3	mA		7
Logic High Output Supply Current	IDDH		0.8	1.3	mA		7
Propagation Delay Time to Logic Low Output	tPHL		46	80	ns	IF = 2 mA, VI = 5 V, RT = 1.68 k, CL = 15 pF, CMOS Signal Levels; or VI = 3.3 V, RT = 870, CL = 15 pF	8
Propagation Delay Time to Logic High Output	tPLH		40	80	ns	IF = 2 mA, VI = 5 V, RT = 1.68 k, CL = 15 pF, CMOS Signal Levels; or VI = 3.3 V, RT = 870, CL = 15 pF	8
Pulse Width	tPW	100			ns		8
Pulse Width Distortion	PWD		6	30	ns		8
Propagation Delay Skew	tPSK			30	ns		8
Output Rise Time (10% - 90%)	tR			12	ns	IF = 2 mA, VI = 5 V, RT = 1.68 k, CL = 15 pF, CMOS Signal Levels	8
Output Rise Time (10% - 90%)	tR			10	ns	IF = 2 mA, VI = 3.3 V, RT = 870, CL = 15 pF, CMOS Signal Levels	8
Output Fall Time (90% - 10%)	tF			12	ns	IF = 2 mA, VI = 5 V, RT = 1.68 k, CL = 15 pF, CMOS Signal Levels	8
Output Fall Time (90% - 10%)	tF			10	ns	IF = 2 mA, VI = 3.3 V, RT = 870, CL = 15 pF, CMOS Signal Levels	8
Static Common Mode Transient Immunity at Logic High Output	CMH	20	35		kV/µs	VCM = 1000 V, TA = 25°C, IF = 0 mA, VI = 0 V (RT = 1.68 k) or (RT = 870), CL = 15 pF, CMOS Signal Levels	8
Static Common Mode Transient Immunity at Logic Low Output	CML	20	35		kV/µs	VCM = 1000 V, TA = 25°C, VI = 5 V (RT = 1.68 k) or VI = 3.3 V (RT = 870), IF = 2 mA, CL = 15 pF, CMOS Signal Levels	8
Dynamic Common Mode Transient Immunity	CMRD		35		kV/µs	VCM = 1000 V, TA = 25°C, IF = 2 mA, VI = 5 V (RT = 1.68 k) or VI = 3.3 V (RT = 870), 10 MBd datarate, absolute increase of PWD < 10 ns	8
Input-Output Insulation	VISO	3750			Vrms	RH < 50% for 1 min., TA = 25°C	9
Input-Output Capacitance	CI-O		0.6		pF	f = 1 MHz, TA = 25°C	9
Input Capacitance	CIN		60		pF	f = 1 MHz, VF = 0 V	7
Input Diode Temperature Coefficient	VF/TA		-1.6		mV/°C	IF = 2 mA	7

CAD (KiCad official)

Symbol: ACPL-061L-500E
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: acpl-061l-500e-etched.step / acpl-061l-500e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); acpl-061l-500e.step / acpl-061l-500e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Broadcom AVAGO datasheet (17 pp, sha256 a7df20103dbe2929, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF