component
LWT1H10AM
Public Made by Adomby adom
Lewa Micro MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLWT1H10AM
Lewa Micro · MOSFETs · SOT-23
LWT1H10AM from Lewa Micro, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate; gate-to-source voltage rated at ±12V maximum, threshold VGS(TH) 1.5V min / 1.8V typ at ID=250µA. |
| 2 | S | passive | Source; body-diode anode side, continuous current 1.0A at TA=25°C and pulsed drain current 3.0A. |
| 3 | D | passive | Drain; drain-to-source voltage rated at 100V maximum, continuous drain current 1.0A at TA=25°C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Lewa Micro |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Voltage | VDSS | 100 | V | 1 | |||
| Gate-to-Source Voltage | VGS | -12 | 12 | V | 1 | ||
| Continuous Drain Current | ID | 1 | A | TA=25℃ | 1 | ||
| Continuous Drain Current | ID | 0.63 | A | TA=100℃ | 1 | ||
| Pulsed Drain Current | IDM | 3 | A | a1: Repetitive rating; pulse width limited by maximum junction temperature | 1 | ||
| Power Dissipation | PD | 0.95 | W | 1 | |||
| Operating Junction and Storage Temperature Range | TJ, TSTG | -55 | 150 | ℃ | 1 | ||
| Maximum Temperature for Soldering | TL | 260 | ℃ | 1 | |||
| Thermal Resistance, Junction-to-Ambient | RθJA | 132 | ℃/W | a2: Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 μm thick) copper area for drain connection. | 1 | ||
| Drain to Source Breakdown Voltage | V(BR)DSS | 100 | V | VGS=0V, ID=250µA | 2 | ||
| Drain to Source Leakage Current | IDSS | 1 | µA | VDS=100V, VGS=0V | 2 | ||
| Gate to Source Forward Leakage | IGSS(F) | 100 | nA | VGS=+12V, VDS=0V | 2 | ||
| Gate to Source Reverse Leakage | IGSS(R) | -100 | nA | VGS=-12V, VDS=0V | 2 | ||
| Gate Threshold Voltage | VGS(TH) | 1.5 | 1.8 | 2.3 | V | VDS=VGS, ID=250µA | 2 |
| Drain-to-Source On-Resistance | RDS(ON)1 | 370 | 450 | mΩ | VGS=10V, ID=1.0A | 2 | |
| Drain-to-Source On-Resistance | RDS(ON)2 | 420 | 550 | mΩ | VGS=4.5V, ID=1.0A | 2 | |
| Diode Forward Voltage | VSD | 1 | V | IS=1.0A, VGS=0V | 2 |
CAD (KiCad official)
- Symbol:
LWT1H10AM - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
lwt1h10am-etched.step/lwt1h10am-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lwt1h10am.step/lwt1h10am.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Lewa Micro datasheet (10 pp, sha256
d84e29514af2173f, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).