component
TPH8R80ANH
Public Made by Adomby adom
TOSHIBA MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPH8R80ANH
TOSHIBA · MOSFETs · SOP-8
TPH8R80ANH from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal (pins 1, 2, 3 are Source) of the N-channel MOSFET, with VDSS of 100 V. |
| 2 | S | passive | Source terminal (pins 1, 2, 3 are Source) of the N-channel MOSFET, with VDSS of 100 V. |
| 3 | S | passive | Source terminal (pins 1, 2, 3 are Source) of the N-channel MOSFET, with VDSS of 100 V. |
| 4 | G | input | Gate terminal with gate-source voltage limit of ±20 V and threshold Vth of 2.0 to 4.0 V (VDS = 10 V, ID = 0.5 mA). |
| 5 | D | passive | Drain terminal (pins 5, 6, 7, 8 are Drain) with 100 V drain-source rating and RDS(ON) of 7.4 mΩ typ. at VGS = 10 V. |
| 6 | D | passive | Drain terminal (pins 5, 6, 7, 8 are Drain) with 100 V drain-source rating and RDS(ON) of 7.4 mΩ typ. at VGS = 10 V. |
| 7 | D | passive | Drain terminal (pins 5, 6, 7, 8 are Drain) with 100 V drain-source rating and RDS(ON) of 7.4 mΩ typ. at VGS = 10 V. |
| 8 | D | passive | Drain terminal (pins 5, 6, 7, 8 are Drain) with 100 V drain-source rating and RDS(ON) of 7.4 mΩ typ. at VGS = 10 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDSS | 100 | V | 1 | |||
| Gate-source voltage | VGSS | -20 | 20 | V | 1 | ||
| Drain current (DC), silicon limit | ID | 59 | A | Silicon limit, Tc = 25 | 1 | ||
| Drain current (DC) | ID | 32 | A | Tc = 25 | 1 | ||
| Drain current (pulsed) | IDP | 139 | A | t = 1 ms | 1 | ||
| Power dissipation | PD | 61 | W | Tc = 25 | 1 | ||
| Power dissipation | PD | 2.8 | W | t = 10 s, Note 3 | 1 | ||
| Power dissipation | PD | 1.6 | W | t = 10 s, Note 4 | 1 | ||
| Single-pulse avalanche energy | EAS | 79 | mJ | VDD = 60 V, Tch = 25 (initial), L = 0.084 mH, RG = 1.0 Ω, IAR = 32 A | 1 | ||
| Avalanche current | IAR | 32 | A | 1 | |||
| Channel temperature | Tch | 150 | °C | 1 | |||
| Storage temperature | Tstg | -55 | 150 | °C | 1 | ||
| Channel-to-case thermal resistance | Rth(ch-c) | 2.04 | °C/W | Tc = 25 | 2 | ||
| Channel-to-ambient thermal resistance | Rth(ch-a) | 44.6 | °C/W | t = 10 s, Note 3 | 2 | ||
| Channel-to-ambient thermal resistance | Rth(ch-a) | 78.1 | °C/W | t = 10 s, Note 4 | 2 | ||
| Gate leakage current | IGSS | -0.1 | 0.1 | µA | VGS = ±20 V, VDS = 0 V | 3 | |
| Drain cut-off current | IDSS | 10 | µA | VDS = 100 V, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage | V(BR)DSS | 100 | V | ID = 10 mA, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage | V(BR)DSX | 65 | V | ID = 10 mA, VGS = -20 V | 3 | ||
| Gate threshold voltage | Vth | 2 | 4 | V | VDS = 10 V, ID = 0.5 mA | 3 | |
| Drain-source on-resistance | RDS(ON) | 7.4 | 8.8 | mΩ | VGS = 10 V, ID = 16 A | 3 | |
| Input capacitance | Ciss | 2180 | 2800 | pF | VDS = 50 V, VGS = 0 V, f = 1 MHz | 3 | |
| Reverse transfer capacitance | Crss | 21 | pF | VDS = 50 V, VGS = 0 V, f = 1 MHz | 3 | ||
| Output capacitance | Coss | 410 | pF | VDS = 50 V, VGS = 0 V, f = 1 MHz | 3 | ||
| Gate resistance | rg | 0.8 | 1.2 | Ω | VDS = 50 V, VGS = 0 V, f = 1 MHz | 3 | |
| Reverse drain current (pulsed) | IDRP | 139 | A | 3 | |||
| Diode forward voltage | VDSF | -1.2 | V | IDR = 32 A, VGS = 0 V | 3 | ||
| Switching time (rise time) | tr | 7 | ns | See Figure 6.2.1 | 3 | ||
| Switching time (turn-on time) | ton | 19 | ns | See Figure 6.2.1 | 3 | ||
| Switching time (fall time) | tf | 12 | ns | See Figure 6.2.1 | 3 | ||
| Switching time (turn-off time) | toff | 33 | ns | See Figure 6.2.1 | 3 | ||
| Total gate charge | Qg | 33 | nC | VDD ≈ 50 V, VGS = 10 V, ID = 32 A | 3 | ||
| Gate-source charge 1 | Qgs1 | 12 | nC | VDD ≈ 50 V, VGS = 10 V, ID = 32 A | 3 | ||
| Gate-drain charge | Qgd | 7.8 | nC | VDD ≈ 50 V, VGS = 10 V, ID = 32 A | 3 | ||
| Gate switch charge | QSW | 13 | nC | VDD ≈ 50 V, VGS = 10 V, ID = 32 A | 3 |
CAD (KiCad official)
- Symbol:
TPH8R80ANH - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tph8r80anh-etched.step/tph8r80anh-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tph8r80anh.step/tph8r80anh.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (9 pp, sha256
2b27189eaac35386, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).