12 V to 5 V / 1 A Buck Molecule (TPS54202), built in Altium Designer

{
 "board": "12 V to 5 V / 1 A buck (TI TPS54202 synchronous buck, 500 kHz), Altium Designer, 28 x 20 mm Adom molecule, 2 layers, medium machine pins on a 24 x 16 mm grid",
 "chains": [
  {
   "direction": "down",
   "refs": [
    "R1",
    "R2",
    "C9"
   ]
  }
 ],
 "clearance": 0.15,
 "copperNote": "1 oz (35 um) finished outer copper, the weight the 3rdPartyFab rules pack is specified for; order the board as 1 oz. Rev A assumed 0.5 oz (17.5 um) as a self-set conservative case, but at U1's 0.95 mm pin pitch the SW copper at pin 2 cannot exceed about 0.9 mm, so 1 A cannot meet the 60 A/mm2 screen at 0.5 oz in any layout (65 A/mm2 there). The 60 A/mm2 limit is unchanged.",
 "copperUm": 35,
 "edgeClearance": 0.3,
 "fab": {
  "rules": "adom-3rdpartyfab",
  "target": "fab",
  "copperOz": 1
 },
 "fabNote": "3rd party fab (3rdPartyFab rules pack, loaded by `rules use`), 2-layer, 1.6 mm FR4",
 "fixedRefs": [
  "MP1",
  "MP2",
  "MP3",
  "MP4",
  "J1",
  "J2",
  "J3",
  "J4",
  "J5",
  "J6"
 ],
 "fixedRefsNote": "the molecule interface: four corner machine pins (GND) and six contacts on the 2 mm grid; everything that connects to the molecule depends on these positions",
 "frameNote": "Coordinates are in the Altium board's frame (reference board shifted by (-98, -102)).",
 "hot": {
  "L1": {
   "tabNet": "VOUT",
   "watts": 0.12
  },
  "U1": {
   "note": "SOT-23-6 has no exposed pad: heat leaves through the pins, mostly GND (pin 1, low-side source) and VIN (pin 3)",
   "tabNet": "GND",
   "watts": 0.25
  }
 },
 "hotMaxRiseC": 55,
 "hotMaxRiseNote": "Approved 2026-09-29 (junction-based): the budget is the pin/tab rise in STILL air. U1 +44 C at its GND pin; psi_JB 33.7 C/W x 0.25 W adds about 8 C to the junction, so Tj is about ambient + 52 C: 92 C at a 40 C ambient, 33 C under the 125 C rating. L1 +41 C is inside its -40..+125 C rating including self-heating. In moving air (25 W/m2K) both are under 30 C (U1 +24, L1 +21). A 28 x 20 mm board losing 0.37 W to still air averages about +33 C even with perfect copper, so 30 C still air is area-limited, not layout-limited: adding 8 more GND vias at the nearest free spots (2.6 to 3.8 mm from U1.1) changed U1 by 0 C in the Fields solve, so they were not added.",
 "hotNote": "U1: I^2R at the hot Rds(on) (1.4 x 148 / 78 mOhm) over the duty at 12 V: 0.15 W, plus about 0.09 W switching (15 ns edges, 500 kHz) and gate drive: 0.25 W. L1: 1.01 A RMS squared x 118 mOhm max DCR = 0.12 W.",
 "inheritedErrors": 0,
 "kelvin": {
  "R1.1": "C6.1",
  "R3.2": "U1.1"
 },
 "kelvinNote": "datasheet 7.4.1: the feedback divider's ground returns to the IC GND pin on its own trace, and the top of the divider senses VOUT at the output capacitor, not along the load current path",
 "loads": {
  "GND": {
   "amps": 1.0,
   "maxRiseC": 10
  },
  "SW": {
   "amps": 1.0,
   "maxRiseC": 10
  },
  "VIN": {
   "amps": 0.6,
   "maxRiseC": 10
  },
  "VOUT": {
   "amps": 1.0,
   "maxRiseC": 10
  }
 },
 "loadsNote": "VIN is the input current at the 9 V low end of the range (5 W / 0.93 / 9 V = 0.6 A); SW carries the inductor RMS current, 1.01 A",
 "midNets": {
  "BOOT": [
   0.3,
   0.2
  ]
 },
 "molecule": {
  "cornerPinsNet": "GND",
  "edgeMarginMm": 2,
  "gridMm": 2,
  "pin": "medium"
 },
 "notPoured": [
  "BOOT",
  "FB",
  "FBM",
  "EN",
  "VMON",
  "LED"
 ],
 "notPouredNote": "bootstrap (dv/dt), the feedback network (high impedance, keep it small and away from SW), the enable and monitor dividers; SW only as the small patch above",
 "planeUnder": [
  {
   "layer": "B.Cu",
   "name": "GND under the input hot loop",
   "net": "GND",
   "polygon": [
    [
     13.5,
     -19.1
    ],
    [
     18.4,
     -19.1
    ],
    [
     18.4,
     -9.4
    ],
    [
     14.1,
     -9.4
    ],
    [
     14.1,
     -12.7
    ],
    [
     13.5,
     -12.7
    ]
   ]
  },
  {
   "layer": "F.Cu",
   "net": "SW",
   "name": "SW node reserved on F.Cu (U1.2 to L1.1, the C5 bootstrap leg above U1's GND pocket, TP1)",
   "polygon": [
    [
     14.3,
     -8.15
    ],
    [
     18.0,
     -8.15
    ],
    [
     18.0,
     -9.1
    ],
    [
     20.1,
     -9.1
    ],
    [
     20.1,
     -12.9
    ],
    [
     16.6,
     -12.9
    ],
    [
     15.85,
     -11.48
    ],
    [
     15.3,
     -11.48
    ],
    [
     15.3,
     -10.55
    ],
    [
     17.0,
     -10.55
    ],
    [
     17.0,
     -8.85
    ],
    [
     14.3,
     -8.85
    ]
   ]
  },
  {
   "layer": "F.Cu",
   "net": "GND",
   "name": "U1 GND pocket on F.Cu (pin 1 to its two stitch vias)",
   "polygon": [
    [
     14.4,
     -9.05
    ],
    [
     16.8,
     -9.05
    ],
    [
     16.8,
     -10.45
    ],
    [
     14.4,
     -10.45
    ]
   ]
  }
 ],
 "planeUnderNote": "the input hot loop runs from C2/C3/C4 to U1 VIN (pin 3) and GND (pin 1), all on the right of U1; B.Cu under it stays GND so the loop's return images directly beneath it. The polygon covers the three input caps and narrows to U1 pins 1 and 3 below y 89.3, leaving U1's left pins (FB, EN, BOOT) a way down to B.Cu.",
 "planes": {},
 "pours": [
  {
   "connection": "thermal",
   "layers": [
    "F.Cu",
    "B.Cu"
   ],
   "name": "GND both layers",
   "net": "GND",
   "outline": true,
   "priority": 0,
   "thermalBridge": 0.35,
   "thermalGap": 0.25
  },
  {
   "connection": "solid",
   "layers": [
    "F.Cu"
   ],
   "name": "VIN input loop F.Cu",
   "net": "VIN",
   "priority": 2,
   "polygon": [
    [
     3.0,
     -19.3
    ],
    [
     16.3,
     -19.3
    ],
    [
     16.3,
     -11.15
    ],
    [
     0.85,
     -11.15
    ],
    [
     0.85,
     -16.6
    ],
    [
     3.0,
     -16.6
    ]
   ],
   "note": "explicit outline (was around J1, C1-C4, U1.3 + 0.5 mm): trimmed off the board-edge strip beside MP3, where it left a 0.09 mm sliver"
  },
  {
   "around": [
    "L1.2",
    "C6.1",
    "C7.1",
    "C8.1",
    "J4",
    "TP3"
   ],
   "connection": "solid",
   "layers": [
    "F.Cu"
   ],
   "margin": 0.5,
   "name": "VOUT output F.Cu",
   "net": "VOUT",
   "priority": 2
  },
  {
   "connection": "solid",
   "layers": [
    "F.Cu"
   ],
   "name": "SW node patch F.Cu (U1.2 to L1.1, squared clear of U1's GND pocket)",
   "net": "SW",
   "polygon": [
    [
     15.3,
     -11.48
    ],
    [
     15.85,
     -11.48
    ],
    [
     16.6,
     -12.9
    ],
    [
     20.1,
     -12.9
    ],
    [
     20.1,
     -9.1
    ],
    [
     17.0,
     -9.1
    ],
    [
     17.0,
     -10.55
    ],
    [
     15.3,
     -10.55
    ]
   ],
   "priority": 3
  }
 ],
 "poursNote": "The input hot loop (C2/C3/C4 -> U1 VIN -> U1 GND -> C GND) stays on F.Cu over an unbroken B.Cu GND; SW is a short wide trace only, never a pour, to keep the switching node's area (and its radiated field) small. Rev 2 (after the Fields solve): a small solid SW patch between U1.2 and L1.1 removes the 0.27 mm neck while keeping the node's area small; U1's GND pin gets a solid connection and three thermal vias into the B.Cu ground plane (it is the IC's main heat path); the inductor pads connect solid.",
 "requireEvidence": [
  "calcs",
  "simulation"
 ],
 "solidAt": [
  "U1.1",
  "U1.3",
  "L1.1",
  "L1.2"
 ],
 "sourcing": {
  "profile": "fab"
 },
 "stitchVias": [
  {
   "net": "GND",
   "x": 15.7,
   "y": -9.25,
   "size": 0.6,
   "drill": 0.3
  },
  {
   "net": "GND",
   "x": 17.55,
   "y": -13.55,
   "size": 0.6,
   "drill": 0.3
  }
 ],
 "stitchViasNote": "GND via at (15.7,-9.25) in the F.Cu pocket beside U1 pin 1, next to the routed pocket via at (16.3,-9.6): pin 1's heat and return path into the B.Cu plane, no via in the SOT-23 pad; one more beside C4.2.",
 "wideNets": {
  "GND": [
   0.8,
   0.5,
   0.3
  ],
  "SW": [
   0.8,
   0.5,
   0.3
  ],
  "VIN": [
   0.8,
   0.5,
   0.3
  ],
  "VOUT": [
   0.8,
   0.5,
   0.3
  ]
 },
 "planeUnderSwNote": "Rev B routing: the first route wrapped SW round U1 pin 1 (GND), cutting the pin off from the F.Cu GND pour (Fields: 202 A/mm2 neck). SW is reserved to a band above the pocket and the patch below it; the pocket beside pin 1 is reserved for GND."
}