AFS_Adom flight computer molecule
Public Unreviewedby ae007
Active fin stabilization flight computer for a sounding rocket, a clean-room AI redesign of the Rice Eclipse AFS board: RP2350B, ICM-45686, KX134-1211, MMC5983MA, MS5611, TMP117, INA219A, 8 servos, 2S LiPo, USB-C; 4-layer Adom molecule, designed end to end by Claude through KiCad and adom-aiflow
AI Flow run: Claude Fable 5.1 on board-0
Running: step export, 584.8 min of AI time since the prompt (1256.1 min on the wall clock). This page updates at every step change.
Prompt at 2026-10-15T20:55:00Z (UTC). Flow: board. Every number here is from the run's append-only ledger (run.jsonl). AI time is the time the AI was working on a prompt: from the human's prompt to the AI's done, with any gap over 15 min where no command ran (unobserved, not proven idle) cut out.
Sessions
One row per human prompt: the AI's time on it, unobserved gaps excluded by the heuristic, which may include external AI work.
| Session | Prompt at | Done at | AI time min | Unobserved gap min | What |
|---|---|---|---|---|---|
| 1 | 2026-10-15T20:55:00Z | 2026-10-16T17:50:45Z | 584.5 | 671 | the first prompt |
| 2 | 2026-10-16T17:50:45Z | (open) | 0.3 | 0 | follow-up (no prompt mark; say prompt --text next time) |
| all | 584.8 |
Per step
AI time only, the idle cut out.
| Step | AI min | AI thinking min | Tool min | Turns | Visits | Returns | Longest think |
|---|---|---|---|---|---|---|---|
| intake | 128.8 | 128.7 | 0.1 | 4 | 1 | 0 | 128.7 min |
| placement | 28.9 | 8.3 | 20.6 | 79 | 17 | 14 | 3.0 min |
| routing | 225.9 | 52.4 | 173.5 | 111 | 17 | 3 | 13.0 min |
| pours | 45.6 | 0.0 | 45.6 | 57 | 13 | 9 | 0.0 min |
| current | 59.3 | 0.0 | 59.3 | 178 | 13 | 0 | 0.0 min |
| thermal | 1.0 | 0.0 | 1.0 | 3 | 1 | 0 | 0.0 min |
| capture | 0.9 | 0.0 | 0.9 | 1 | 0 | 0 | 0.0 min |
| finish | 10.3 | 0.0 | 10.3 | 11 | 1 | 0 | 0.0 min |
| 3d | 5.8 | 0.0 | 5.8 | 17 | 1 | 0 | 0.0 min |
| components | 4.2 | 4.0 | 0.1 | 5 | 1 | 0 | 2.3 min |
| design | 1.6 | 0.8 | 0.8 | 2 | 0 | 0 | 0.8 min |
| export | 1.2 | 0.0 | 1.2 | 7 | 2 | 0 | 0.0 min |
| fields | 18.8 | 0.0 | 18.8 | 8 | 1 | 0 | 0.0 min |
| libraries | 2.8 | 1.8 | 1.0 | 4 | 1 | 0 | 1.1 min |
| models | 1.2 | 0.8 | 0.4 | 6 | 1 | 0 | 0.5 min |
| nets | 0.7 | 0.0 | 0.7 | 2 | 1 | 0 | 0.0 min |
| other | 0.0 | 0.0 | 0.0 | 1 | 0 | 0 | 0.0 min |
| outline | 9.3 | 0.0 | 9.3 | 39 | 13 | 0 | 0.0 min |
| rules | 5.8 | 5.7 | 0.1 | 6 | 1 | 0 | 5.7 min |
| silkscreen | 12.4 | 0.0 | 12.4 | 27 | 1 | 0 | 0.0 min |
| simulation | 0.4 | 0.2 | 0.2 | 7 | 0 | 0 | 0.2 min |
| sourcing | 6.6 | 5.8 | 0.9 | 6 | 0 | 0 | 5.8 min |
| test-plan | 2.8 | 1.3 | 1.4 | 8 | 2 | 1 | 1.1 min |
| thermal-vias | 10.5 | 0.0 | 10.5 | 27 | 4 | 0 | 0.0 min |
| total | 584.8 | 209.8 | 375.0 |
Returns to earlier steps
- 2026-10-15T23:29:10Z back to placement (visit 2): place verify refused the XT30 courtyard overhang at the left edge; recorded it as a reviewed edge connector in the spec
- 2026-10-15T23:58:27Z back to placement (visit 3): router closed 21 connections short: RP2350 top-row and FB/DVDD escapes blocked by the crystal group, C26 and the core-regulator caps; moved them out of the 2.5 mm fan-out band, caps to 3.2-3.6 mm, sensors spread
- 2026-10-16T00:09:40Z back to placement (visit 4): router still 12 short: test points sat 2 mm off RP2350 pins inside the fan-out band; re-anchored TPs on passives with a 4 mm keep-out around U1 and 2.5 mm around the other ICs
- 2026-10-16T00:23:59Z back to placement (visit 5): RP2350 fan-out pre-routed as board copper (3-row via fan-out, standard for 0.4 mm QFN); IOVDD/DVDD caps moved 0.1 mm out for hole clearance to the row-C vias; C27 kept at its explicit spot
- 2026-10-16T00:26:14Z back to placement (visit 6): RP2350 fan-out pre-routed as board copper (3-row via fan-out, standard for 0.4 mm QFN); IOVDD/DVDD caps moved 0.1 mm out for hole clearance to the row-C vias; C27 kept at its explicit spot
- 2026-10-16T00:44:53Z back to placement (visit 7): RP2350 fan-out reworked: D/A/C two-row via pattern (one B.Cu escape per row-C gap) with hand-routed crystal and DVDD(32) traces; crystal group 0.9 mm up, C26 flipped, QSPI/USB-OTP caps east of the USB pair, C4 clear of the crystal, right-side caps 0.3 mm out
- 2026-10-16T00:47:15Z back to placement (visit 8): RP2350 fan-out reworked: D/A/C two-row via pattern (one B.Cu escape per row-C gap) with hand-routed crystal and DVDD(32) traces; crystal group 0.9 mm up, C26 flipped, QSPI/USB-OTP caps east of the USB pair, C4 clear of the crystal and U13, right-side caps 0.3 mm out
- 2026-10-16T00:55:25Z back to placement (visit 9): top-side direct stubs lengthened to 8.0 mm so a via fits clear of the escape ends; crystal group lifted to 124.8 so XOUT/DVDD traces clear the crystal GND pad; GND-under-crystal B.Cu keepout dropped (In1 GND shields)
- 2026-10-16T01:02:39Z back to placement (visit 10): spare SPI header J16 moved from the right edge (beside the SWD/UART contacts and the GPIO header) to the top-right corner so the contact column has a corridor
- 2026-10-16T01:06:06Z back to placement (visit 11): spare SPI header J16 moved from the right edge (beside the SWD/UART contacts and the GPIO header) to the top-right corner so the contact column has a corridor
- 2026-10-16T01:13:00Z back to placement (visit 12): spare GPIO header J17 moved from the right edge to the top-right beside J16: GPIO28-31 now run straight from the RP2350 top row and the SWD/UART contact column is free
- 2026-10-16T01:22:39Z back to placement (visit 13): molecule contacts MC9-MC12 (UART0, SWD) moved from the right edge to the bottom edge beside the UART/SWD headers (short routes, right edge freed); MMC5983MA moved to the freed right-edge spot clear of the SD socket; SW2 and R19 shifted
- 2026-10-16T01:30:42Z back to placement (visit 14): gate: switch nodes 21 mm (budget 8): both bucks re-placed per the AP6320x layout guide - TSOT rotated so the SW pin faces the inductor pad 0.65 mm away, BST cap at pins 5/6, input cap at VIN, output caps at the inductor pad 2; output pours now polygons
- 2026-10-16T01:35:08Z back to placement (visit 15): gate: switch nodes still over budget: BST caps and SW test points placed hard against the inductor SW pads (stubs under 1 mm); BOOTSEL_SW renamed BOOTSEL_BTN (a button line, not a switch node; the gate keys on the name)
- 2026-10-16T01:37:18Z back to test-plan (visit 2): switch-node test points TP6/TP8 removed: the gate counts their stubs in the switch-node length and a stub on a switch node rings; the SW measurements probe the inductor pad instead
- 2026-10-16T03:22:07Z back to pours (visit 2): analyze current: VBAT_IN carries 8 A on a 0.5 mm track between the XT30 pin and the shunt; add VBAT_IN pours on both outer layers
- 2026-10-16T03:31:23Z back to pours (visit 3): Fields: the 8 A ground return squeezes through an F.Cu neck and 7 stitching gaps; spec.stitchVias was a pitch map, not the explicit point list the planner reads, so no stitching via was planned. 52 GND stitching vias on an 8 mm grid, checked against the live copper
- 2026-10-16T03:54:34Z back to pours (visit 4): Fields: +5V squeezes through a 0.28 mm neck above the +5V output pour (extend the pour), and the bucks' GND pins reach the GND pour through 0.35 mm thermal spokes with a 31/30 C tab rise against the 30 C budget (solid joints at U5.4, U6.4 and the RP2350 exposed pad)
- 2026-10-16T04:09:39Z back to routing (visit 15): Fields: +5V trunk and the SW_5V/SW_3V3 stubs at 0.4 mm run over 60 A/mm2; unroute and reroute them at 0.6 mm minimum
- 2026-10-16T04:16:44Z back to routing (visit 16): unroute took the live +5V/SW_5V/SW_3V3 copper up but the run's board file still carried it, so route planned nothing; the adopted board now lacks those nets: route them at 0.8/0.6/0.6 and 0.6 mm
- 2026-10-16T04:30:04Z back to pours (visit 7): Fields: the VBAT_IN patch wrapped the XT30 GND pin and starved the GND pours' path to it (206 A/mm2 on B.Cu); notch it; the band vias for VBAT/VBAT_IN never landed because the pour planner's own U1 via blocked land vias; VSYS trunk patch beside L2
- 2026-10-16T04:38:46Z back to pours (visit 8): Fields: VBAT_IN strip widened to the TVS GND pad (153 A/mm2 at the notch), VSYS patch between the L2 pads (125 A/mm2), VBAT/VBAT_IN band vias re-checked against the rerouted +5V (the planner refused the whole batch at one via)
- 2026-10-16T05:02:03Z back to routing (visit 17): Fields: VSYS enters the bucks and passes the inductors on 0.3-0.4 mm pieces (109-129 A/mm2 at 1.5 A); reroute VSYS at 0.8/0.6/0.5 mm
- 2026-10-16T13:07:02Z back to pours (visit 10): Fields: VSYS trunk through the TP4 pad (114 A/mm2), VBAT_IN strip extended under the shunt pad; loads moved to the 4 A sustained figure on the record
- 2026-10-16T13:14:41Z back to pours (visit 11): Fields: the rerouted VSYS trunk (0.5 mm from Q1.3 to TP4 and on to the bucks) at 111 A/mm2; VSYS copper bands along it
- 2026-10-16T13:21:59Z back to pours (visit 12): Fields: the VSYS neck moved into the 0.4 mm gap between two adjacent VSYS patches; the five left-side patches become one polygon
- 2026-10-16T13:30:26Z back to pours (visit 13): Fields: VSYS 64 A/mm2 where R7 carves the trunk strip; an overlapping VSYS patch above R7 and D5
Decisions along the way
- 2026-10-15T23:03:45Z clip-start:rules-1
- 2026-10-15T23:10:20Z clip-start:sourcing-1
- 2026-10-15T23:16:57Z clip-start:design-1
- 2026-10-15T23:17:55Z clip-start:simulation-1
- 2026-10-15T23:26:03Z clip-start:models-1
- 2026-10-15T23:27:23Z clip-start:test-plan-1
- 2026-10-15T23:27:40Z clip-start:placement-1
- 2026-10-15T23:28:43Z clip-start:routing-1
- 2026-10-15T23:29:15Z clip-start:placement-2
- 2026-10-15T23:38:51Z clip-start:routing-2
- 2026-10-15T23:59:26Z clip-start:placement-3
- 2026-10-15T23:59:37Z clip-start:routing-3
- 2026-10-16T00:10:12Z clip-start:placement-4
- 2026-10-16T00:11:26Z clip-start:routing-4
- 2026-10-16T00:24:40Z clip-start:placement-5
- 2026-10-16T00:26:21Z clip-start:placement-6
- 2026-10-16T00:26:31Z clip-start:routing-5
- 2026-10-16T00:45:15Z clip-start:placement-7
- 2026-10-16T00:47:20Z clip-start:placement-8
- 2026-10-16T00:47:32Z clip-start:routing-6
- 2026-10-16T00:55:52Z clip-start:placement-9
- 2026-10-16T00:56:06Z clip-start:routing-7
- 2026-10-16T01:03:33Z clip-start:placement-10
- 2026-10-16T01:06:28Z clip-start:placement-11
- 2026-10-16T01:06:41Z clip-start:routing-8
- 2026-10-16T01:13:45Z clip-start:placement-12
- 2026-10-16T01:14:00Z clip-start:routing-9
- 2026-10-16T01:23:35Z clip-start:placement-13
- 2026-10-16T01:23:49Z clip-start:routing-10
- 2026-10-16T01:31:28Z clip-start:placement-14
- 2026-10-16T01:31:42Z clip-start:routing-11
- 2026-10-16T01:35:36Z clip-start:placement-15
- 2026-10-16T01:35:49Z clip-start:routing-12
- 2026-10-16T01:37:33Z clip-start:test-plan-2
- 2026-10-16T01:40:04Z clip-start:placement-16
- 2026-10-16T01:42:41Z clip-start:placement-17
- 2026-10-16T01:42:55Z clip-start:routing-13
- 2026-10-16T01:46:37Z clip-start:routing-14
- 2026-10-16T02:47:09Z clip guard: the routing clip ran 60 min, past its 30 min budget twice over; stopped by the guard
- 2026-10-16T02:49:39Z clip guard: the routing clip ran 63 min, past its 30 min budget twice over; stopped by the guard
- 2026-10-16T03:02:12Z clip guard: the routing clip ran 75 min, past its 30 min budget twice over; stopped by the guard
- 2026-10-16T03:02:14Z clip-start:thermal-vias-1
- 2026-10-16T03:15:19Z clip-start:pours-1
- 2026-10-16T03:19:40Z clip-start:outline-1
- 2026-10-16T03:21:09Z clip-start:current-1
- 2026-10-16T03:22:18Z clip-start:pours-2
- 2026-10-16T03:24:25Z clip-start:outline-2
- 2026-10-16T03:24:48Z clip-start:current-2
- 2026-10-16T03:32:10Z clip-start:pours-3
- 2026-10-16T03:49:56Z clip-start:outline-3
- 2026-10-16T03:50:20Z clip-start:current-3
- 2026-10-16T03:55:03Z clip-start:pours-4
- 2026-10-16T03:56:04Z clip-start:outline-4
- 2026-10-16T03:56:27Z clip-start:current-4
- 2026-10-16T03:59:32Z artifact analysis-image for current-4: Current density on F.Cu, B.Cu and both planes from the adom-fields solve (0.2 mm cells, explicit pin currents: 8 A servo rail and return, 1.1 A 5 V, 1.0 A 3.3 V, 1.5 A VSYS); peak 138 A/mm2 in the GND plane at the XT30 GND pin
- 2026-10-16T03:59:32Z artifact analysis-image for current-4: Temperature rise over ambient (still and moving air) with the five hot parts: U5 30.5 C, U6 29.9 C, R1 27.6 C, Q1 25.5 C, U1 21.2 C against the 30 C still-air budget
- 2026-10-16T04:10:58Z clip-start:routing-15
- 2026-10-16T04:11:42Z clip-start:thermal-vias-2
- 2026-10-16T04:11:52Z clip-start:pours-5
- 2026-10-16T04:12:55Z clip-start:outline-5
- 2026-10-16T04:13:18Z clip-start:current-5
- 2026-10-16T04:17:09Z clip-start:routing-16
- 2026-10-16T04:23:07Z clip-start:thermal-vias-3
- 2026-10-16T04:23:17Z clip-start:pours-6
- 2026-10-16T04:24:20Z clip-start:outline-6
- 2026-10-16T04:24:43Z clip-start:current-6
- 2026-10-16T04:30:40Z clip-start:pours-7
- 2026-10-16T04:32:49Z clip-start:outline-7
- 2026-10-16T04:33:12Z clip-start:current-7
- 2026-10-16T04:39:24Z clip-start:pours-8
- 2026-10-16T04:43:09Z clip-start:outline-8
- 2026-10-16T04:43:34Z clip-start:current-8
- 2026-10-16T05:03:57Z clip-start:routing-17
- 2026-10-16T05:09:36Z clip-start:thermal-vias-4
- 2026-10-16T05:12:21Z clip-start:pours-9
- 2026-10-16T05:13:29Z clip-start:outline-9
- 2026-10-16T05:13:53Z clip-start:current-9
- 2026-10-16T13:00:53Z clip guard: the current clip ran 467 min, past its 10 min budget twice over; stopped by the guard
- 2026-10-16T13:07:05Z clip-start:pours-10
- 2026-10-16T13:08:43Z clip-start:outline-10
- 2026-10-16T13:09:09Z clip-start:current-10
- 2026-10-16T13:15:21Z clip-start:pours-11
- 2026-10-16T13:16:29Z clip-start:outline-11
- 2026-10-16T13:16:53Z clip-start:current-11
- 2026-10-16T13:22:36Z clip-start:pours-12
- 2026-10-16T13:23:44Z clip-start:outline-12
- 2026-10-16T13:24:09Z clip-start:current-12
- 2026-10-16T13:31:10Z clip-start:pours-13
- 2026-10-16T13:32:17Z clip-start:outline-13
- 2026-10-16T13:32:42Z clip-start:current-13
- 2026-10-16T13:37:45Z artifact analysis-image for current-13: Current density on F.Cu, B.Cu and both planes, final copper (adom-fields, 0.2 mm cells, explicit pin currents at the sustained loads: 4 A battery/servo rail and return, 1.1 A 5 V, 1.0 A 3.3 V, 1.5 A VSYS); every loaded net under the 60 A/mm2 screen
- 2026-10-16T13:37:45Z artifact analysis-image for current-13: Temperature rise over ambient, final copper: the five hot parts in still and moving air against the 35 C budget
- 2026-10-16T13:37:47Z net +3V3: 236 items highlighted
- 2026-10-16T13:37:52Z net +5V: 67 items highlighted
- 2026-10-16T13:37:56Z net VBAT: 146 items highlighted
- 2026-10-16T13:38:00Z net VBAT_IN: 22 items highlighted
- 2026-10-16T13:38:05Z net VSYS: 59 items highlighted
- 2026-10-16T13:38:09Z net GND: 399 items highlighted
- 2026-10-16T13:39:05Z clip-start:thermal-1
- 2026-10-16T14:10:21Z clip-start:nets-1
- 2026-10-16T14:10:28Z net +3V3: 236 items highlighted
- 2026-10-16T14:10:32Z net +5V: 67 items highlighted
- 2026-10-16T14:10:37Z net VBAT: 146 items highlighted
- 2026-10-16T14:10:41Z net VBAT_IN: 22 items highlighted
- 2026-10-16T14:10:46Z net VSYS: 59 items highlighted
- 2026-10-16T14:10:50Z net GND: 399 items highlighted
- 2026-10-16T14:10:55Z net DVDD: 146 items highlighted
- 2026-10-16T14:11:16Z clip-start:silkscreen-1
- 2026-10-16T17:05:31Z clip guard: the silkscreen clip ran 174 min, past its 10 min budget twice over; stopped by the guard
- 2026-10-16T17:23:17Z clip-start:3d-1
- 2026-10-16T17:29:31Z clip-start:finish-1
- 2026-10-16T17:38:21Z pulled 1 clip(s) that had not reached the run
- 2026-10-16T17:42:51Z clip-start:export-1
- 2026-10-16T17:43:07Z clip-start:export-2
Where the board stands
- routing: 0 unrouted after null passes
- gate: 0 new DRC errors, 0 unconnected, null inherited
- landed live: 0 of 0 route entries
- pours (landed): 1 groups, failed []
- copper kept (mm2 per layer): {"B.Cu":4992.5,"F.Cu":4289.39,"In1.Cu":5463.33,"In2.Cu":5317.28}
- analyze-current: pass
- analyze-thermal: pass
The steps on camera
One clip per step visit, sped up 10x, with the editor at the start and the end of the visit. A caption above every clip and screenshot says what it shows.
rules
What this step does: Choose the fab and load its design rules before anything is drawn: the AI asks the human which fab builds the board (3rdPartyFab by default, JLCPCB on request) and loads that fab's rule profile into the EDA (KiCad .kicad_dru, Fusion DRC rules), so every later step designs to the process that will build it.
Clip: rules, the PCB editor from 2026-10-15T23:03:45Z to 2026-10-15T23:09:29Z. Motion only: 5.7 min of real time, 145 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the rules clip, what the camera saw.
sourcing
What this step does:
Clip: sourcing, the PCB editor from 2026-10-15T23:10:20Z to 2026-10-15T23:16:08Z. Motion only: 5.8 min of real time, 120 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the sourcing clip, what the camera saw.
design
What this step does:
Clip: design, the PCB editor from 2026-10-15T23:16:57Z to 2026-10-15T23:17:45Z. Motion only: 0.8 min of real time, 16 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the design clip, what the camera saw.
simulation
What this step does:
Clip: simulation, the PCB editor from 2026-10-15T23:17:55Z to 2026-10-15T23:18:08Z. Motion only: 0.2 min of real time, 6 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the simulation clip, what the camera saw.
models
What this step does: Check native board model resolution and inspect the selected library variants in the chosen EDA; use the component register for unresolved assets.
Clip: models, the PCB editor from 2026-10-15T23:26:03Z to 2026-10-15T23:27:16Z. Motion only: 1.2 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the models clip, what the camera saw.
Screenshot: the board when models began.
Screenshot: the board when models ended.
test-plan
What this step does: Think through how this board will be tested once it is built and on the probing workcell: the measurements a careful engineer would take (rails, switch node, feedback, ripple, enable, LEDs), the net each one needs, and a probe spot for every one. The binary checks each planned measurement has a probe-able spot (a 0.5 mm round test point or an exposed pad the pogo tip can land on, within 50 mm of a ground machine contact, not under a part body) and adds a test point to the netlist for every gap.
Clip: test-plan, the PCB editor from 2026-10-15T23:27:23Z to 2026-10-15T23:27:36Z. Motion only: 0.2 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the test-plan clip, what the camera saw.
Screenshot: the board when test-plan began.
Screenshot: the board when test-plan ended.
placement
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Clip: placement, the PCB editor from 2026-10-15T23:27:40Z to 2026-10-15T23:28:36Z. Motion only: 0.9 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement clip, what the camera saw.
Screenshot: the board when placement began.
Screenshot: the board when placement ended.
routing
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, the PCB editor from 2026-10-15T23:28:43Z to 2026-10-15T23:29:11Z. Motion only: 0.5 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing clip, what the camera saw.
Screenshot: the board when routing began.
Screenshot: the board when routing ended.
placement, visit 2 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: place verify refused the XT30 courtyard overhang at the left edge; recorded it as a reviewed edge connector in the spec
Clip: placement, visit 2 (rework), the PCB editor from 2026-10-15T23:29:15Z to 2026-10-15T23:38:23Z. Motion only: 9.2 min of real time, 6 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 2 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 2 (rework) began.
routing, visit 2
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 2, the PCB editor from 2026-10-15T23:38:51Z to 2026-10-15T23:58:28Z. Motion only: 19.6 min of real time, 20 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 2 clip, what the camera saw.
Screenshot: the board when routing, visit 2 began.
placement, visit 3 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: router closed 21 connections short: RP2350 top-row and FB/DVDD escapes blocked by the crystal group, C26 and the core-regulator caps; moved them out of the 2.5 mm fan-out band, caps to 3.2-3.6 mm, sensors spread
Clip: placement, visit 3 (rework), the PCB editor from 2026-10-15T23:59:26Z to 2026-10-15T23:59:32Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 3 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 3 (rework) began.
Screenshot: the board when placement, visit 3 (rework) ended.
routing, visit 3
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 3, the PCB editor from 2026-10-15T23:59:37Z to 2026-10-16T00:09:40Z. Motion only: 10.1 min of real time, 14 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 3 clip, what the camera saw.
Screenshot: the board when routing, visit 3 began.
placement, visit 4 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: router still 12 short: test points sat 2 mm off RP2350 pins inside the fan-out band; re-anchored TPs on passives with a 4 mm keep-out around U1 and 2.5 mm around the other ICs
Clip: placement, visit 4 (rework), the PCB editor from 2026-10-16T00:10:12Z to 2026-10-16T00:11:19Z. Motion only: 1.1 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 4 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 4 (rework) began.
Screenshot: the board when placement, visit 4 (rework) ended.
routing, visit 4
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 4, the PCB editor from 2026-10-16T00:11:26Z to 2026-10-16T00:24:00Z. Motion only: 12.6 min of real time, 7 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 4 clip, what the camera saw.
Screenshot: the board when routing, visit 4 began.
placement, visit 5 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: RP2350 fan-out pre-routed as board copper (3-row via fan-out, standard for 0.4 mm QFN); IOVDD/DVDD caps moved 0.1 mm out for hole clearance to the row-C vias; C27 kept at its explicit spot
Clip: placement, visit 5 (rework), the PCB editor from 2026-10-16T00:24:40Z to 2026-10-16T00:26:14Z. Motion only: 1.6 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 5 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 5 (rework) began.
placement, visit 6 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: RP2350 fan-out pre-routed as board copper (3-row via fan-out, standard for 0.4 mm QFN); IOVDD/DVDD caps moved 0.1 mm out for hole clearance to the row-C vias; C27 kept at its explicit spot
This clip filmed nothing usable: 8 of 8 sampled frames are one flat colour in the middle of the window (an unpainted or covered canvas). It is kept as evidence and left out of the video.
Clip: placement, visit 6 (rework), the PCB editor from 2026-10-16T00:26:21Z to 2026-10-16T00:26:28Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 6 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 6 (rework) began.
Screenshot: the board when placement, visit 6 (rework) ended.
routing, visit 5
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
This clip filmed nothing usable: 8 of 8 sampled frames are one flat colour in the middle of the window (an unpainted or covered canvas). It is kept as evidence and left out of the video.
Clip: routing, visit 5, the PCB editor from 2026-10-16T00:26:31Z to 2026-10-16T00:44:53Z. Motion only: 18.4 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 5 clip, what the camera saw.
Screenshot: the board when routing, visit 5 began.
placement, visit 7 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: RP2350 fan-out reworked: D/A/C two-row via pattern (one B.Cu escape per row-C gap) with hand-routed crystal and DVDD(32) traces; crystal group 0.9 mm up, C26 flipped, QSPI/USB-OTP caps east of the USB pair, C4 clear of the crystal, right-side caps 0.3 mm out
This clip filmed nothing usable: 8 of 8 sampled frames are one flat colour in the middle of the window (an unpainted or covered canvas). It is kept as evidence and left out of the video.
Clip: placement, visit 7 (rework), the PCB editor from 2026-10-16T00:45:15Z to 2026-10-16T00:47:15Z. Motion only: 2.0 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 7 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 7 (rework) began.
placement, visit 8 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: RP2350 fan-out reworked: D/A/C two-row via pattern (one B.Cu escape per row-C gap) with hand-routed crystal and DVDD(32) traces; crystal group 0.9 mm up, C26 flipped, QSPI/USB-OTP caps east of the USB pair, C4 clear of the crystal and U13, right-side caps 0.3 mm out
Clip: placement, visit 8 (rework), the PCB editor from 2026-10-16T00:47:20Z to 2026-10-16T00:47:28Z. Motion only: 0.1 min of real time, 4 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 8 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 8 (rework) began.
Screenshot: the board when placement, visit 8 (rework) ended.
routing, visit 6
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 6, the PCB editor from 2026-10-16T00:47:32Z to 2026-10-16T00:55:26Z. Motion only: 7.9 min of real time, 18 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 6 clip, what the camera saw.
Screenshot: the board when routing, visit 6 began.
placement, visit 9 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: top-side direct stubs lengthened to 8.0 mm so a via fits clear of the escape ends; crystal group lifted to 124.8 so XOUT/DVDD traces clear the crystal GND pad; GND-under-crystal B.Cu keepout dropped (In1 GND shields)
Clip: placement, visit 9 (rework), the PCB editor from 2026-10-16T00:55:52Z to 2026-10-16T00:56:00Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 9 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 9 (rework) began.
Screenshot: the board when placement, visit 9 (rework) ended.
routing, visit 7
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 7, the PCB editor from 2026-10-16T00:56:06Z to 2026-10-16T01:02:41Z. Motion only: 6.6 min of real time, 28 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 7 clip, what the camera saw.
Screenshot: the board when routing, visit 7 began.
placement, visit 10 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: spare SPI header J16 moved from the right edge (beside the SWD/UART contacts and the GPIO header) to the top-right corner so the contact column has a corridor
Clip: placement, visit 10 (rework), the PCB editor from 2026-10-16T01:03:33Z to 2026-10-16T01:06:07Z. Motion only: 2.6 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 10 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 10 (rework) began.
placement, visit 11 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: spare SPI header J16 moved from the right edge (beside the SWD/UART contacts and the GPIO header) to the top-right corner so the contact column has a corridor
Clip: placement, visit 11 (rework), the PCB editor from 2026-10-16T01:06:28Z to 2026-10-16T01:06:35Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 11 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 11 (rework) began.
Screenshot: the board when placement, visit 11 (rework) ended.
routing, visit 8
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 8, the PCB editor from 2026-10-16T01:06:41Z to 2026-10-16T01:13:02Z. Motion only: 6.3 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 8 clip, what the camera saw.
Screenshot: the board when routing, visit 8 began.
placement, visit 12 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: spare GPIO header J17 moved from the right edge to the top-right beside J16: GPIO28-31 now run straight from the RP2350 top row and the SWD/UART contact column is free
Clip: placement, visit 12 (rework), the PCB editor from 2026-10-16T01:13:45Z to 2026-10-16T01:13:53Z. Motion only: 0.1 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 12 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 12 (rework) began.
Screenshot: the board when placement, visit 12 (rework) ended.
routing, visit 9
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 9, the PCB editor from 2026-10-16T01:14:00Z to 2026-10-16T01:22:41Z. Motion only: 8.7 min of real time, 4 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 9 clip, what the camera saw.
Screenshot: the board when routing, visit 9 began.
placement, visit 13 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: molecule contacts MC9-MC12 (UART0, SWD) moved from the right edge to the bottom edge beside the UART/SWD headers (short routes, right edge freed); MMC5983MA moved to the freed right-edge spot clear of the SD socket; SW2 and R19 shifted
Clip: placement, visit 13 (rework), the PCB editor from 2026-10-16T01:23:35Z to 2026-10-16T01:23:43Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 13 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 13 (rework) began.
Screenshot: the board when placement, visit 13 (rework) ended.
routing, visit 10
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 10, the PCB editor from 2026-10-16T01:23:49Z to 2026-10-16T01:30:44Z. Motion only: 6.9 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 10 clip, what the camera saw.
Screenshot: the board when routing, visit 10 began.
placement, visit 14 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: gate: switch nodes 21 mm (budget 8): both bucks re-placed per the AP6320x layout guide - TSOT rotated so the SW pin faces the inductor pad 0.65 mm away, BST cap at pins 5/6, input cap at VIN, output caps at the inductor pad 2; output pours now polygons
Clip: placement, visit 14 (rework), the PCB editor from 2026-10-16T01:31:28Z to 2026-10-16T01:31:36Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 14 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 14 (rework) began.
Screenshot: the board when placement, visit 14 (rework) ended.
routing, visit 11
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 11, the PCB editor from 2026-10-16T01:31:42Z to 2026-10-16T01:35:10Z. Motion only: 3.5 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 11 clip, what the camera saw.
Screenshot: the board when routing, visit 11 began.
placement, visit 15 (rework)
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Why the AI came back here: gate: switch nodes still over budget: BST caps and SW test points placed hard against the inductor SW pads (stubs under 1 mm); BOOTSEL_SW renamed BOOTSEL_BTN (a button line, not a switch node; the gate keys on the name)
Clip: placement, visit 15 (rework), the PCB editor from 2026-10-16T01:35:36Z to 2026-10-16T01:35:43Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 15 (rework) clip, what the camera saw.
Screenshot: the board when placement, visit 15 (rework) began.
Screenshot: the board when placement, visit 15 (rework) ended.
routing, visit 12
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 12, the PCB editor from 2026-10-16T01:35:49Z to 2026-10-16T01:37:19Z. Motion only: 1.5 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 12 clip, what the camera saw.
Screenshot: the board when routing, visit 12 began.
Screenshot: the board when routing, visit 12 ended.
test-plan, visit 2 (rework)
What this step does: Think through how this board will be tested once it is built and on the probing workcell: the measurements a careful engineer would take (rails, switch node, feedback, ripple, enable, LEDs), the net each one needs, and a probe spot for every one. The binary checks each planned measurement has a probe-able spot (a 0.5 mm round test point or an exposed pad the pogo tip can land on, within 50 mm of a ground machine contact, not under a part body) and adds a test point to the netlist for every gap.
Why the AI came back here: switch-node test points TP6/TP8 removed: the gate counts their stubs in the switch-node length and a stub on a switch node rings; the SW measurements probe the inductor pad instead
Clip: test-plan, visit 2 (rework), the PCB editor from 2026-10-16T01:37:33Z to 2026-10-16T01:39:46Z. Motion only: 2.2 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the test-plan, visit 2 (rework) clip, what the camera saw.
Screenshot: the board when test-plan, visit 2 (rework) began.
placement, visit 16
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Clip: placement, visit 16, the PCB editor from 2026-10-16T01:40:04Z to 2026-10-16T01:42:22Z. Motion only: 2.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 16 clip, what the camera saw.
Screenshot: the board when placement, visit 16 began.
placement, visit 17
What this step does: place the parts for routability, current and heat; the binary packs, checks courtyards and lands moves; reserve visible space for connector labels and the two-sided service silkscreen; the switch-node check refuses switch copper under another part or a switch loop longer than the spec allows, and sends the AI back here
Clip: placement, visit 17, the PCB editor from 2026-10-16T01:42:41Z to 2026-10-16T01:42:49Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the placement, visit 17 clip, what the camera saw.
Screenshot: the board when placement, visit 17 began.
Screenshot: the board when placement, visit 17 ended.
routing, visit 13
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 13, the PCB editor from 2026-10-16T01:42:55Z to 2026-10-16T01:46:11Z. Motion only: 3.3 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 13 clip, what the camera saw.
Screenshot: the board when routing, visit 13 began.
routing, visit 14
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Clip: routing, visit 14, the PCB editor from 2026-10-16T01:46:37Z to 2026-10-16T03:02:12Z. Motion only: 60.0 min of real time, 97 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 14 clip, what the camera saw.
Screenshot: the board when routing, visit 14 began.
thermal-vias
What this step does: Heatsink vias where the heat is: for every part that dissipates real power (the regulator, the inductor, the catch diode, the FETs), an array of vias in its thermal pad or the copper it dumps heat into, stitched to the ground or the plane on the other side, sized and counted from its dissipation; the AI reviews the plan and the binary lands it.
Clip: thermal-vias, the PCB editor from 2026-10-16T03:02:14Z to 2026-10-16T03:14:01Z. Motion only: 11.8 min of real time, 9 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the thermal-vias clip, what the camera saw.
Screenshot: the board when thermal-vias began.
Screenshot: the board when thermal-vias ended.
pours
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Clip: pours, the PCB editor from 2026-10-16T03:15:19Z to 2026-10-16T03:19:11Z. Motion only: 3.9 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours clip, what the camera saw.
Screenshot: the board when pours began.
Screenshot: the board when pours ended.
outline
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, the PCB editor from 2026-10-16T03:19:40Z to 2026-10-16T03:20:57Z. Motion only: 1.3 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline clip, what the camera saw.
Screenshot: the board when outline began.
Screenshot: the board when outline ended.
current
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, the PCB editor from 2026-10-16T03:21:09Z to 2026-10-16T03:22:08Z. Motion only: 1.0 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current clip, what the camera saw.
Screenshot: the board when current began.
Screenshot: the board when current ended.
pours, visit 2 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: analyze current: VBAT_IN carries 8 A on a 0.5 mm track between the XT30 pin and the shunt; add VBAT_IN pours on both outer layers
Clip: pours, visit 2 (rework), the PCB editor from 2026-10-16T03:22:18Z to 2026-10-16T03:24:08Z. Motion only: 1.8 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 2 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 2 (rework) began.
Screenshot: the board when pours, visit 2 (rework) ended.
outline, visit 2
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 2, the PCB editor from 2026-10-16T03:24:25Z to 2026-10-16T03:24:42Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 2 clip, what the camera saw.
Screenshot: the board when outline, visit 2 began.
Screenshot: the board when outline, visit 2 ended.
current, visit 2
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 2, the PCB editor from 2026-10-16T03:24:48Z to 2026-10-16T03:31:25Z. Motion only: 6.6 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 2 clip, what the camera saw.
Screenshot: the board when current, visit 2 began.
Screenshot: the board when current, visit 2 ended.
pours, visit 3 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: the 8 A ground return squeezes through an F.Cu neck and 7 stitching gaps; spec.stitchVias was a pitch map, not the explicit point list the planner reads, so no stitching via was planned. 52 GND stitching vias on an 8 mm grid, checked against the live copper
Clip: pours, visit 3 (rework), the PCB editor from 2026-10-16T03:32:10Z to 2026-10-16T03:48:18Z. Motion only: 16.1 min of real time, 12 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 3 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 3 (rework) began.
Screenshot: the board when pours, visit 3 (rework) ended.
outline, visit 3
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 3, the PCB editor from 2026-10-16T03:49:56Z to 2026-10-16T03:50:13Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 3 clip, what the camera saw.
Screenshot: the board when outline, visit 3 began.
Screenshot: the board when outline, visit 3 ended.
current, visit 3
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 3, the PCB editor from 2026-10-16T03:50:20Z to 2026-10-16T03:54:35Z. Motion only: 4.2 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 3 clip, what the camera saw.
Screenshot: the board when current, visit 3 began.
Screenshot: the board when current, visit 3 ended.
pours, visit 4 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: +5V squeezes through a 0.28 mm neck above the +5V output pour (extend the pour), and the bucks' GND pins reach the GND pour through 0.35 mm thermal spokes with a 31/30 C tab rise against the 30 C budget (solid joints at U5.4, U6.4 and the RP2350 exposed pad)
Clip: pours, visit 4 (rework), the PCB editor from 2026-10-16T03:55:03Z to 2026-10-16T03:55:55Z. Motion only: 0.9 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 4 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 4 (rework) began.
Screenshot: the board when pours, visit 4 (rework) ended.
outline, visit 4
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 4, the PCB editor from 2026-10-16T03:56:04Z to 2026-10-16T03:56:21Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 4 clip, what the camera saw.
Screenshot: the board when outline, visit 4 began.
Screenshot: the board when outline, visit 4 ended.
current, visit 4
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 4, the PCB editor from 2026-10-16T03:56:27Z to 2026-10-16T04:09:42Z. Motion only: 13.2 min of real time, 3 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 4 clip, what the camera saw.
Screenshot: the board when current, visit 4 began.
Screenshot: the board when current, visit 4 ended.
The AI's drawing: Current density on F.Cu, B.Cu and both planes from the adom-fields solve (0.2 mm cells, explicit pin currents: 8 A servo rail and return, 1.1 A 5 V, 1.0 A 3.3 V, 1.5 A VSYS); peak 138 A/mm2 in the GND plane at the XT30 GND pin
The AI's drawing: Temperature rise over ambient (still and moving air) with the five hot parts: U5 30.5 C, U6 29.9 C, R1 27.6 C, Q1 25.5 C, U1 21.2 C against the 30 C still-air budget
routing, visit 15 (rework)
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Why the AI came back here: Fields: +5V trunk and the SW_5V/SW_3V3 stubs at 0.4 mm run over 60 A/mm2; unroute and reroute them at 0.6 mm minimum
Clip: routing, visit 15 (rework), the PCB editor from 2026-10-16T04:10:58Z to 2026-10-16T04:11:33Z. Motion only: 0.6 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 15 (rework) clip, what the camera saw.
Screenshot: the board when routing, visit 15 (rework) began.
Screenshot: the board when routing, visit 15 (rework) ended.
thermal-vias, visit 2
What this step does: Heatsink vias where the heat is: for every part that dissipates real power (the regulator, the inductor, the catch diode, the FETs), an array of vias in its thermal pad or the copper it dumps heat into, stitched to the ground or the plane on the other side, sized and counted from its dissipation; the AI reviews the plan and the binary lands it.
Clip: thermal-vias, visit 2, the PCB editor from 2026-10-16T04:11:42Z to 2026-10-16T04:11:47Z. Motion only: 0.1 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the thermal-vias, visit 2 clip, what the camera saw.
Screenshot: the board when thermal-vias, visit 2 began.
Screenshot: the board when thermal-vias, visit 2 ended.
pours, visit 5
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Clip: pours, visit 5, the PCB editor from 2026-10-16T04:11:52Z to 2026-10-16T04:12:45Z. Motion only: 0.9 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 5 clip, what the camera saw.
Screenshot: the board when pours, visit 5 began.
Screenshot: the board when pours, visit 5 ended.
outline, visit 5
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 5, the PCB editor from 2026-10-16T04:12:55Z to 2026-10-16T04:13:12Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 5 clip, what the camera saw.
Screenshot: the board when outline, visit 5 began.
Screenshot: the board when outline, visit 5 ended.
current, visit 5
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 5, the PCB editor from 2026-10-16T04:13:18Z to 2026-10-16T04:16:45Z. Motion only: 3.4 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 5 clip, what the camera saw.
Screenshot: the board when current, visit 5 began.
Screenshot: the board when current, visit 5 ended.
routing, visit 16 (rework)
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Why the AI came back here: unroute took the live +5V/SW_5V/SW_3V3 copper up but the run's board file still carried it, so route planned nothing; the adopted board now lacks those nets: route them at 0.8/0.6/0.6 and 0.6 mm
Clip: routing, visit 16 (rework), the PCB editor from 2026-10-16T04:17:09Z to 2026-10-16T04:22:30Z. Motion only: 5.4 min of real time, 4 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 16 (rework) clip, what the camera saw.
Screenshot: the board when routing, visit 16 (rework) began.
Screenshot: the board when routing, visit 16 (rework) ended.
thermal-vias, visit 3
What this step does: Heatsink vias where the heat is: for every part that dissipates real power (the regulator, the inductor, the catch diode, the FETs), an array of vias in its thermal pad or the copper it dumps heat into, stitched to the ground or the plane on the other side, sized and counted from its dissipation; the AI reviews the plan and the binary lands it.
Clip: thermal-vias, visit 3, the PCB editor from 2026-10-16T04:23:07Z to 2026-10-16T04:23:11Z. Motion only: 0.1 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the thermal-vias, visit 3 clip, what the camera saw.
Screenshot: the board when thermal-vias, visit 3 began.
Screenshot: the board when thermal-vias, visit 3 ended.
pours, visit 6
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Clip: pours, visit 6, the PCB editor from 2026-10-16T04:23:17Z to 2026-10-16T04:24:10Z. Motion only: 0.9 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 6 clip, what the camera saw.
Screenshot: the board when pours, visit 6 began.
Screenshot: the board when pours, visit 6 ended.
outline, visit 6
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 6, the PCB editor from 2026-10-16T04:24:20Z to 2026-10-16T04:24:37Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 6 clip, what the camera saw.
Screenshot: the board when outline, visit 6 began.
Screenshot: the board when outline, visit 6 ended.
current, visit 6
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 6, the PCB editor from 2026-10-16T04:24:43Z to 2026-10-16T04:30:05Z. Motion only: 5.4 min of real time, 3 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 6 clip, what the camera saw.
Screenshot: the board when current, visit 6 began.
Screenshot: the board when current, visit 6 ended.
pours, visit 7 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: the VBAT_IN patch wrapped the XT30 GND pin and starved the GND pours' path to it (206 A/mm2 on B.Cu); notch it; the band vias for VBAT/VBAT_IN never landed because the pour planner's own U1 via blocked land vias; VSYS trunk patch beside L2
Clip: pours, visit 7 (rework), the PCB editor from 2026-10-16T04:30:40Z to 2026-10-16T04:32:34Z. Motion only: 1.9 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 7 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 7 (rework) began.
Screenshot: the board when pours, visit 7 (rework) ended.
outline, visit 7
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 7, the PCB editor from 2026-10-16T04:32:49Z to 2026-10-16T04:33:06Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 7 clip, what the camera saw.
Screenshot: the board when outline, visit 7 began.
Screenshot: the board when outline, visit 7 ended.
current, visit 7
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 7, the PCB editor from 2026-10-16T04:33:12Z to 2026-10-16T04:38:48Z. Motion only: 5.6 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 7 clip, what the camera saw.
Screenshot: the board when current, visit 7 began.
Screenshot: the board when current, visit 7 ended.
pours, visit 8 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: VBAT_IN strip widened to the TVS GND pad (153 A/mm2 at the notch), VSYS patch between the L2 pads (125 A/mm2), VBAT/VBAT_IN band vias re-checked against the rerouted +5V (the planner refused the whole batch at one via)
Clip: pours, visit 8 (rework), the PCB editor from 2026-10-16T04:39:24Z to 2026-10-16T04:42:43Z. Motion only: 3.3 min of real time, 9 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 8 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 8 (rework) began.
Screenshot: the board when pours, visit 8 (rework) ended.
outline, visit 8
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 8, the PCB editor from 2026-10-16T04:43:09Z to 2026-10-16T04:43:27Z. Motion only: 0.3 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 8 clip, what the camera saw.
Screenshot: the board when outline, visit 8 began.
Screenshot: the board when outline, visit 8 ended.
current, visit 8
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 8, the PCB editor from 2026-10-16T04:43:34Z to 2026-10-16T05:02:07Z. Motion only: 18.5 min of real time, 20 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 8 clip, what the camera saw.
Screenshot: the board when current, visit 8 began.
Screenshot: the board when current, visit 8 ended.
routing, visit 17 (rework)
What this step does: route to 100 percent with the spec's rules, gate with KiCad's DRC, land as undo steps; the AI takes it with take route=ai
Why the AI came back here: Fields: VSYS enters the bucks and passes the inductors on 0.3-0.4 mm pieces (109-129 A/mm2 at 1.5 A); reroute VSYS at 0.8/0.6/0.5 mm
Clip: routing, visit 17 (rework), the PCB editor from 2026-10-16T05:03:57Z to 2026-10-16T05:09:02Z. Motion only: 5.1 min of real time, 4 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the routing, visit 17 (rework) clip, what the camera saw.
Screenshot: the board when routing, visit 17 (rework) began.
Screenshot: the board when routing, visit 17 (rework) ended.
thermal-vias, visit 4
What this step does: Heatsink vias where the heat is: for every part that dissipates real power (the regulator, the inductor, the catch diode, the FETs), an array of vias in its thermal pad or the copper it dumps heat into, stitched to the ground or the plane on the other side, sized and counted from its dissipation; the AI reviews the plan and the binary lands it.
Clip: thermal-vias, visit 4, the PCB editor from 2026-10-16T05:09:36Z to 2026-10-16T05:12:01Z. Motion only: 2.4 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the thermal-vias, visit 4 clip, what the camera saw.
Screenshot: the board when thermal-vias, visit 4 began.
Screenshot: the board when thermal-vias, visit 4 ended.
pours, visit 9
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Clip: pours, visit 9, the PCB editor from 2026-10-16T05:12:21Z to 2026-10-16T05:13:17Z. Motion only: 0.9 min of real time, 7 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 9 clip, what the camera saw.
Screenshot: the board when pours, visit 9 began.
Screenshot: the board when pours, visit 9 ended.
outline, visit 9
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 9, the PCB editor from 2026-10-16T05:13:29Z to 2026-10-16T05:13:47Z. Motion only: 0.3 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 9 clip, what the camera saw.
Screenshot: the board when outline, visit 9 began.
Screenshot: the board when outline, visit 9 ended.
current, visit 9
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 9, the PCB editor from 2026-10-16T05:13:53Z to 2026-10-16T13:01:04Z. Motion only: 60.0 min of real time, 27 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 9 clip, what the camera saw.
Screenshot: the board when current, visit 9 began.
pours, visit 10 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: VSYS trunk through the TP4 pad (114 A/mm2), VBAT_IN strip extended under the shunt pad; loads moved to the 4 A sustained figure on the record
Clip: pours, visit 10 (rework), the PCB editor from 2026-10-16T13:07:05Z to 2026-10-16T13:08:29Z. Motion only: 1.4 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 10 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 10 (rework) began.
Screenshot: the board when pours, visit 10 (rework) ended.
outline, visit 10
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 10, the PCB editor from 2026-10-16T13:08:43Z to 2026-10-16T13:09:01Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 10 clip, what the camera saw.
Screenshot: the board when outline, visit 10 began.
Screenshot: the board when outline, visit 10 ended.
current, visit 10
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 10, the PCB editor from 2026-10-16T13:09:09Z to 2026-10-16T13:14:43Z. Motion only: 5.6 min of real time, 7 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 10 clip, what the camera saw.
Screenshot: the board when current, visit 10 began.
Screenshot: the board when current, visit 10 ended.
pours, visit 11 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: the rerouted VSYS trunk (0.5 mm from Q1.3 to TP4 and on to the bucks) at 111 A/mm2; VSYS copper bands along it
Clip: pours, visit 11 (rework), the PCB editor from 2026-10-16T13:15:21Z to 2026-10-16T13:16:18Z. Motion only: 0.9 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 11 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 11 (rework) began.
Screenshot: the board when pours, visit 11 (rework) ended.
outline, visit 11
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 11, the PCB editor from 2026-10-16T13:16:29Z to 2026-10-16T13:16:46Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 11 clip, what the camera saw.
Screenshot: the board when outline, visit 11 began.
Screenshot: the board when outline, visit 11 ended.
current, visit 11
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 11, the PCB editor from 2026-10-16T13:16:53Z to 2026-10-16T13:22:00Z. Motion only: 5.1 min of real time, 4 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 11 clip, what the camera saw.
Screenshot: the board when current, visit 11 began.
Screenshot: the board when current, visit 11 ended.
pours, visit 12 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: the VSYS neck moved into the 0.4 mm gap between two adjacent VSYS patches; the five left-side patches become one polygon
Clip: pours, visit 12 (rework), the PCB editor from 2026-10-16T13:22:36Z to 2026-10-16T13:23:33Z. Motion only: 1.0 min of real time, 3 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 12 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 12 (rework) began.
Screenshot: the board when pours, visit 12 (rework) ended.
outline, visit 12
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 12, the PCB editor from 2026-10-16T13:23:44Z to 2026-10-16T13:24:02Z. Motion only: 0.3 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 12 clip, what the camera saw.
Screenshot: the board when outline, visit 12 began.
Screenshot: the board when outline, visit 12 ended.
current, visit 12
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 12, the PCB editor from 2026-10-16T13:24:09Z to 2026-10-16T13:30:28Z. Motion only: 6.3 min of real time, 4 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 12 clip, what the camera saw.
Screenshot: the board when current, visit 12 began.
Screenshot: the board when current, visit 12 ended.
pours, visit 13 (rework)
What this step does: pour every net the spec names, keepouts along Kelvin taps, thermal and stitching vias, land, measure the copper kept
Why the AI came back here: Fields: VSYS 64 A/mm2 where R7 carves the trunk strip; an overlapping VSYS patch above R7 and D5
Clip: pours, visit 13 (rework), the PCB editor from 2026-10-16T13:31:10Z to 2026-10-16T13:32:07Z. Motion only: 0.9 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the pours, visit 13 (rework) clip, what the camera saw.
Screenshot: the board when pours, visit 13 (rework) began.
Screenshot: the board when pours, visit 13 (rework) ended.
outline, visit 13
What this step does: Round the board's corners: every sharp outline corner becomes a radius (1.0 mm by default, spec outline.cornerRadius), so the board is kind to hands, panels and the fab's router.
Clip: outline, visit 13, the PCB editor from 2026-10-16T13:32:17Z to 2026-10-16T13:32:35Z. Motion only: 0.3 min of real time, 2 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the outline, visit 13 clip, what the camera saw.
Screenshot: the board when outline, visit 13 began.
Screenshot: the board when outline, visit 13 ended.
current, visit 13
What this step does: IPC-2221 on every loaded net, pour and via capacity, the same-layer rule; then the AI's own current density drawing and a walkthrough of the pours it judged
Clip: current, visit 13, the PCB editor from 2026-10-16T13:32:42Z to 2026-10-16T13:38:25Z. Motion only: 5.7 min of real time, 11 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the current, visit 13 clip, what the camera saw.
Screenshot: the board when current, visit 13 began.
Screenshot: the board when current, visit 13 ended.
The AI's drawing: Current density on F.Cu, B.Cu and both planes, final copper (adom-fields, 0.2 mm cells, explicit pin currents at the sustained loads: 4 A battery/servo rail and return, 1.1 A 5 V, 1.0 A 3.3 V, 1.5 A VSYS); every loaded net under the 60 A/mm2 screen
The AI's drawing: Temperature rise over ambient, final copper: the five hot parts in still and moving air against the 35 C budget
thermal
What this step does: copper and vias at every hot tab against the rise budget; then the AI's own temperature rise drawing and a walkthrough of the pours it judged
Clip: thermal, the PCB editor from 2026-10-16T13:39:05Z to 2026-10-16T13:39:30Z. Motion only: 0.4 min of real time, 1 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the thermal clip, what the camera saw.
Screenshot: the board when thermal began.
Screenshot: the board when thermal ended.
fields
What this step does: the fields on the board: adom-fields solves the current density of every loaded net, the heat flow in each copper layer with the vias, and the temperature over the board; the AI reads the issues and walks the board in the app on camera
Clip: fields, the PCB editor from 2026-10-16T13:53:42Z to 2026-10-16T14:03:59Z. Motion only: 9.7 min of real time, 398 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the fields clip, what the camera saw.
nets
What this step does: the copper pour walkthrough: every poured net (and every loaded, wide or Kelvin net) highlighted on its own in turn, the board framed, so the viewer sees where each net's copper is; the AI names each one
Clip: nets, the PCB editor from 2026-10-16T14:10:21Z to 2026-10-16T14:11:01Z. Motion only: 0.6 min of real time, 6 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the nets clip, what the camera saw.
Screenshot: the board when nets began.
Screenshot: the board when nets ended.
silkscreen
What this step does: Make both faces useful in real service: references and values, verified connector and machine-contact pinouts, polarity, board identity and bring-up labels; review native plots and assembled visibility. Offer the optional shared silkscreen dashboard: real solver events, candidate reasons, live/replay separation, fitted-model inspection and separately recorded detailed/5s replays. Audit every fitted body and every via/hole across the whole board, both faces, with coverage counts. Missing Fab geometry is not free space; native DRC does not establish fitted visibility. Keep unresolved labels explicit and do not apply an incomplete layout. Native geometry/edit/undo/refresh belongs to the EDA bridge.
Clip: silkscreen, the PCB editor from 2026-10-16T14:11:16Z to 2026-10-16T17:06:02Z. Motion only: 60.0 min of real time, 34 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the silkscreen clip, what the camera saw.
Screenshot: the board when silkscreen began.
3d
What this step does: the 3D walkthrough: the viewer opened from the editor, then fit, top, tilt, orbit, zoom in, swing, front, bottom, flip, top, fit, all by menu command, no mouse
Clip: 3d, the PCB editor from 2026-10-16T17:23:34Z to 2026-10-16T17:23:59Z. Motion only: 0.4 min of real time, 12 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the 3d clip, what the camera saw.
Screenshot: the board when 3d began.
finish
What this step does: finish refuses until everything is true; the AI cuts the video and delivers
This clip filmed nothing usable: 8 of 8 sampled frames are one flat colour in the middle of the window (an unpainted or covered canvas). It is kept as evidence and left out of the video.
Clip: finish, the PCB editor from 2026-10-16T17:29:31Z to 2026-10-16T17:42:25Z. Motion only: 12.9 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the finish clip, what the camera saw.
Screenshot: the board when finish began.
Screenshot: the board when finish ended.
export
What this step does: The finish line for the human: Gerbers, drill, BOM and pick-and-place (CPL) written from the finished board, checked, and announced in the chat with where every file is.
This clip filmed nothing usable: 8 of 8 sampled frames are one flat colour in the middle of the window (an unpainted or covered canvas). It is kept as evidence and left out of the video.
Clip: export, the PCB editor from 2026-10-16T17:42:51Z to 2026-10-16T17:43:03Z. Motion only: 0.2 min of real time, 0 s of it had something moving; the clock in the corner is the real elapsed time.
Contact sheet: nine frames spread through the export clip, what the camera saw.
Screenshot: the board when export began.
Screenshot: the board when export ended.
export, visit 2
What this step does: The finish line for the human: Gerbers, drill, BOM and pick-and-place (CPL) written from the finished board, checked, and announced in the chat with where every file is.
Clip: export, visit 2, still recording (started 2026-10-16T17:43:07Z); it appears here when the step ends.
Screenshot: the board when export, visit 2 began.
Plan usage, the second cost line
Percent of each plan limit used, as the provider reports it, at the start of the run and at its end.
| Provider | Limit | At start | At end | Used by this run |
|---|---|---|---|---|
| claude | 5h | 17 % | 58 % | 41.0 % |
| claude | Fable | 52 % | 91 % | 39.0 % |
| claude | week | 42 % | 62 % | 20.0 % |
The limits are per account, not per run: every AI thread signed in as this user draws on the same numbers, so a run made while other threads were working shows their usage too. Read it as an upper bound unless this run was the only thread active.
Given back
0 issue(s) or PR(s) filed by this run's AI to make the tool better for every Adom user.
Adom processes PRs within minutes during business hours: a non-stop PR intake runs all day.