component
ZGAD250S14
Public Made by Adomby adom
Zynalog Analog To Digital Converters (ADCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "zgad250s14",
"title": "ZGAD250S14",
"brief": "Zynalog Analog To Digital Converters (ADCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"adc-dac-data conversion",
"zgad250s14",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "ZGAD250S14",
"manufacturer": "Zynalog",
"package": "QFN-40(6x6)",
"pin_count": 41,
"category": "ADC/DAC/Data Conversion",
"subcategory": "Analog To Digital Converters (ADCs)",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/d938c81ef207be9905ddf99aeaf21085.pdf",
"parts": {
"symbol": "zgad250s14.kicad_sym",
"footprint": "zgad250s14.kicad_mod",
"model_3d": "zgad250s14-hero.glb",
"model_3d_plain": "zgad250s14-etched.glb",
"model_3d_step": "zgad250s14-etched.step",
"model_3d_step_plain": "zgad250s14.step",
"lbr": "zgad250s14.lbr"
},
"distributor_links": {
"lcsc": "C7527745"
},
"distributor_check": {
"checked_at": "2026-11-02T17:47:44Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply input; bypass to ground with a 0.1µF ceramic capacitor, and pins 1 and 2 may share one bypass capacitor."
},
{
"number": "2",
"name": "VDD",
"type": "power_in",
"description": "1.8V analog supply input; bypass to ground with a 0.1µF ceramic capacitor, and pins 1 and 2 may share one bypass capacitor."
},
{
"number": "3",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
},
{
"number": "4",
"name": "Vin+",
"type": "power_in",
"description": "Positive differential analog input; the differential input must stay within 1.5V and be driven 180° out of phase with Vin-, using the VCM common-mode voltage."
},
{
"number": "5",
"name": "Vin-",
"type": "power_in",
"description": "Negative differential analog input; the differential input must stay within 1.5V and be driven 180° out of phase with Vin+, using the VCM common-mode voltage."
},
{
"number": "6",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
},
{
"number": "7",
"name": "SENSE",
"type": "input",
"description": "External reference input: tie to VDD to select the internal reference (±0.75V input range), or drive with an external reference between 1.2V and 1.3V (±0.6*VSENSE input range)."
},
{
"number": "8",
"name": "VREF",
"type": "power_in",
"description": "Reference voltage output, nominally 1.25V; bypass to ground with a 2.2µF ceramic capacitor."
},
{
"number": "9",
"name": "VCM",
"type": "output",
"description": "Common-mode bias output, nominally 0.435*VDD; use it to set the common-mode bias of the analog inputs and bypass to ground with a 0.1µF ceramic capacitor."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
},
{
"number": "11",
"name": "CLK+",
"type": "input",
"description": "Positive sampling clock input; conversion starts on the rising edge of the clock."
},
{
"number": "12",
"name": "CLK-",
"type": "input",
"description": "Negative sampling clock input; conversion starts on the falling edge of the clock."
},
{
"number": "13",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
},
{
"number": "14",
"name": "OF-",
"type": "output",
"description": "Overflow/underflow LVDS output, complementary signal; OF+ is high when an overflow or underflow occurs."
},
{
"number": "15",
"name": "OF+",
"type": "output",
"description": "Overflow/underflow LVDS output; OF+ is high when an overflow or underflow occurs."
},
{
"number": "16",
"name": "D0_1-",
"type": "output",
"description": "DDR LVDS data output, complementary: carries bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
},
{
"number": "17",
"name": "D0_1+",
"type": "output",
"description": "DDR LVDS data output: carries bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
},
{
"number": "18",
"name": "D2_3-",
"type": "output",
"description": "DDR LVDS data output, complementary: carries bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
},
{
"number": "19",
"name": "D2_3+",
"type": "output",
"description": "DDR LVDS data output: carries bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
},
{
"number": "20",
"name": "DVDD",
"type": "power_in",
"description": "1.8V supply for the digital output drivers; bypass each DVDD pin to ground with a separate 0.1µF ceramic capacitor."
},
{
"number": "21",
"name": "DGND",
"type": "power_in",
"description": "Ground for the digital output drivers."
},
{
"number": "22",
"name": "D4_5-",
"type": "output",
"description": "DDR LVDS data output, complementary: carries bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
},
{
"number": "23",
"name": "D4_5+",
"type": "output",
"description": "DDR LVDS data output: carries bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
},
{
"number": "24",
"name": "D6_7-",
"type": "output",
"description": "DDR LVDS data output, complementary: carries bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
},
{
"number": "25",
"name": "D6_7+",
"type": "output",
"description": "DDR LVDS data output: carries bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
},
{
"number": "26",
"name": "CLKOUT-",
"type": "output",
"description": "Data output clock LVDS, complementary; normally switches together with the falling and rising edges of CLKOUT+."
},
{
"number": "27",
"name": "CLKOUT+",
"type": "output",
"description": "Data output clock LVDS; normally switches on the falling and rising edges of the data outputs, and its phase can be delayed relative to the data by register programming."
},
{
"number": "28",
"name": "D8_9-",
"type": "output",
"description": "DDR LVDS data output, complementary: carries bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
},
{
"number": "29",
"name": "D8_9+",
"type": "output",
"description": "DDR LVDS data output: carries bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
},
{
"number": "30",
"name": "DVDD",
"type": "power_in",
"description": "1.8V supply for the digital output drivers; bypass each DVDD pin to ground with a separate 0.1µF ceramic capacitor."
},
{
"number": "31",
"name": "D10_11-",
"type": "output",
"description": "DDR LVDS data output, complementary: carries bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
},
{
"number": "32",
"name": "D10_11+",
"type": "output",
"description": "DDR LVDS data output: carries bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
},
{
"number": "33",
"name": "D12_13-",
"type": "output",
"description": "DDR LVDS data output, complementary: carries bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
},
{
"number": "34",
"name": "D12_13+",
"type": "output",
"description": "DDR LVDS data output: carries bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
},
{
"number": "35",
"name": "GND",
"type": "power_in",
"description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
},
{
"number": "36",
"name": "SPI_MISO",
"type": "output",
"description": "SPI data output in serial mode (MODE=0); open-drain, requires a 2kΩ pull-up to the 1.8V to 3.3V SPI supply when registers are read back, and has no effect in parallel mode."
},
{
"number": "37",
"name": "SPI_MOSI",
"type": "input",
"description": "SPI data input in serial mode (MODE=0); in parallel mode (MODE=VDD) it selects the LVDS output current, 3.5mA when low and 1.75mA when high at 1.8V to 3.3V logic levels."
},
{
"number": "38",
"name": "SPI_SCLK",
"type": "input",
"description": "SPI clock input in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables sleep mode when high at 1.8V to 3.3V logic levels."
},
{
"number": "39",
"name": "SPI_CS",
"type": "input",
"description": "SPI chip select in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables the clock duty cycle stabilizer when high at 1.8V to 3.3V logic levels."
},
{
"number": "40",
"name": "MODE",
"type": "input",
"description": "Serial/parallel mode select: tie to GND for SPI mode or to VDD for parallel GPIO mode; it must be hard-wired to GND or VDD and not driven by a logic signal."
},
{
"number": "41",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
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"guards": "pin_guards 0.1: passed",
"guard_notes": [
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],
"pages_sent": 19,
"cost_usd": 0.0445,
"at": "2026-11-02T17:47:34"
},
"datasheet": {
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"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
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"described": 41,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
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},
"metadata": {
"specs": {
"Manufacturer": "Zynalog",
"Package": "QFN-40(6x6)",
"Category": "ADC/DAC/Data Conversion",
"Pins": "41"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "b85a16310fc2dd7b8b78700cbb4c02329475df9b9b7a04322e9c07a3d5353571",
"rows": [
{
"name": "Analog supply voltage VDD",
"symbol": "VDD",
"kind": "electrical",
"unit": "V",
"min": 1.7,
"typ": 1.8,
"max": 1.9,
"conditions": "",
"source_page": 4,
"source": "datasheet"
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{
"name": "Digital supply voltage DVDD",
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"kind": "electrical",
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"min": 1.7,
"typ": 1.8,
"max": 1.9,
"conditions": "",
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{
"name": "Analog supply input current",
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"min": null,
"typ": 170,
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"source": "datasheet"
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{
"name": "Power dissipation with 1.75mA LVDS output",
"symbol": "P_1.75",
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"min": null,
"typ": 338,
"max": null,
"conditions": "1.75mA LVDS output",
"source_page": 4,
"source": "datasheet"
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{
"name": "Power dissipation with 3.5mA LVDS output",
"symbol": "P_3.5",
"kind": "electrical",
"unit": "mW",
"min": null,
"typ": 378,
"max": null,
"conditions": "3.5mA LVDS output",
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{
"name": "Power dissipation in low power mode",
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"min": null,
"typ": 104,
"max": null,
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"source": "datasheet"
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{
"name": "Power dissipation in sleep mode",
"symbol": "P_sleep",
"kind": "electrical",
"unit": "mW",
"min": null,
"typ": 0.65,
"max": null,
"conditions": "",
"source_page": 4,
"source": "datasheet"
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{
"name": "Integral nonlinearity",
"symbol": "INL",
"kind": "tolerance",
"unit": "LSB",
"min": -2,
"typ": 1,
"max": 2,
"conditions": "",
"source_page": 4,
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{
"name": "Differential nonlinearity",
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"kind": "tolerance",
"unit": "LSB",
"min": -0.6,
"typ": 0.35,
"max": 0.6,
"conditions": "",
"source_page": 4,
"source": "datasheet"
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{
"name": "Offset error",
"symbol": "Offset Error",
"kind": "tolerance",
"unit": "mV",
"min": -13,
"typ": 5,
"max": 13,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Gain error",
"symbol": "Gain Error",
"kind": "tolerance",
"unit": "%FS",
"min": -4,
"typ": 1,
"max": 2.2,
"conditions": "",
"source_page": 4,
"source": "datasheet"
},
{
"name": "Signal-to-noise ratio",
"symbol": "SNR",
"kind": "electrical",
"unit": "dB",
"min": null,
"typ": 70,
"max": null,
"conditions": "",
"source_page": 4,
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},
{
"name": "Spurious-free dynamic range",
"symbol": "SFDR",
"kind": "electrical",
"unit": "dB",
"min": null,
"typ": 90,
"max": null,
"conditions": "",
"source_page": 4,
"source": "datasheet"
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{
"name": "Digital output differential voltage (3.5mA mode)",
"symbol": "V_OD",
"kind": "electrical",
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"min": 247,
"typ": 350,
"max": 454,
"conditions": "3.5mA mode",
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{
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"typ": 175,
"max": 250,
"conditions": "1.75mA mode",
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{
"name": "Digital output common-mode voltage",
"symbol": "V_OS",
"kind": "electrical",
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"min": 1.125,
"typ": 1.25,
"max": 1.375,
"conditions": "",
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{
"name": "Clock input to data acquisition delay",
"symbol": "tAP",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": 1,
"max": null,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
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{
"name": "Clock input high hold time",
"symbol": "tH",
"kind": "timing",
"unit": "ns",
"min": 1.9,
"typ": 2,
"max": null,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
"source_page": 10,
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{
"name": "Clock input low hold time",
"symbol": "tL",
"kind": "timing",
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"min": 1.9,
"typ": 2,
"max": null,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
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{
"name": "Clock input to clock output delay",
"symbol": "tC",
"kind": "timing",
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"min": 1.3,
"typ": 1.6,
"max": 2,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
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{
"name": "Clock input to data output delay",
"symbol": "tD",
"kind": "timing",
"unit": "ns",
"min": 1.7,
"typ": 2,
"max": 2.3,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
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{
"name": "Clock output to data output skew (tC - tD)",
"symbol": "tSKEW",
"kind": "timing",
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"min": 0.3,
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"max": 0.55,
"conditions": "VDD=1.8V, DVDD=1.8V, fS=250MHz",
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{
"name": "CS low to clock setup time",
"symbol": "tS",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": 5,
"max": null,
"conditions": "SPI_MISO pull-up 2KΩ",
"source_page": 15,
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{
"name": "Data setup time",
"symbol": "tDS",
"kind": "timing",
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"min": null,
"typ": 5,
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"conditions": "SPI_MISO pull-up 2KΩ",
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{
"name": "Data hold time",
"symbol": "tDH",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": 5,
"max": null,
"conditions": "SPI_MISO pull-up 2KΩ",
"source_page": 15,
"source": "datasheet"
},
{
"name": "Clock to data output delay",
"symbol": "tDO",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": 125,
"max": null,
"conditions": "SPI_MISO pull-up 2KΩ",
"source_page": 15,
"source": "datasheet"
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