ZGAD250S14 from Zynalog, in a QFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	1.8V analog supply input; bypass to ground with a 0.1µF ceramic capacitor, and pins 1 and 2 may share one bypass capacitor.
2	VDD	power_in	1.8V analog supply input; bypass to ground with a 0.1µF ceramic capacitor, and pins 1 and 2 may share one bypass capacitor.
3	GND	power_in	Power ground; the exposed pad on the back must be soldered to the PCB ground.
4	Vin+	power_in	Positive differential analog input; the differential input must stay within 1.5V and be driven 180° out of phase with Vin-, using the VCM common-mode voltage.
5	Vin-	power_in	Negative differential analog input; the differential input must stay within 1.5V and be driven 180° out of phase with Vin+, using the VCM common-mode voltage.
6	GND	power_in	Power ground; the exposed pad on the back must be soldered to the PCB ground.
7	SENSE	input	External reference input: tie to VDD to select the internal reference (±0.75V input range), or drive with an external reference between 1.2V and 1.3V (±0.6*VSENSE input range).
8	VREF	power_in	Reference voltage output, nominally 1.25V; bypass to ground with a 2.2µF ceramic capacitor.
9	VCM	output	Common-mode bias output, nominally 0.435*VDD; use it to set the common-mode bias of the analog inputs and bypass to ground with a 0.1µF ceramic capacitor.
10	GND	power_in	Power ground; the exposed pad on the back must be soldered to the PCB ground.
11	CLK+	input	Positive sampling clock input; conversion starts on the rising edge of the clock.
12	CLK-	input	Negative sampling clock input; conversion starts on the falling edge of the clock.
13	GND	power_in	Power ground; the exposed pad on the back must be soldered to the PCB ground.
14	OF-	output	Overflow/underflow LVDS output, complementary signal; OF+ is high when an overflow or underflow occurs.
15	OF+	output	Overflow/underflow LVDS output; OF+ is high when an overflow or underflow occurs.
16	D0_1-	output	DDR LVDS data output, complementary: carries bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high.
17	D0_1+	output	DDR LVDS data output: carries bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high.
18	D2_3-	output	DDR LVDS data output, complementary: carries bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high.
19	D2_3+	output	DDR LVDS data output: carries bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high.
20	DVDD	power_in	1.8V supply for the digital output drivers; bypass each DVDD pin to ground with a separate 0.1µF ceramic capacitor.
21	DGND	power_in	Ground for the digital output drivers.
22	D4_5-	output	DDR LVDS data output, complementary: carries bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high.
23	D4_5+	output	DDR LVDS data output: carries bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high.
24	D6_7-	output	DDR LVDS data output, complementary: carries bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high.
25	D6_7+	output	DDR LVDS data output: carries bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high.
26	CLKOUT-	output	Data output clock LVDS, complementary; normally switches together with the falling and rising edges of CLKOUT+.
27	CLKOUT+	output	Data output clock LVDS; normally switches on the falling and rising edges of the data outputs, and its phase can be delayed relative to the data by register programming.
28	D8_9-	output	DDR LVDS data output, complementary: carries bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high.
29	D8_9+	output	DDR LVDS data output: carries bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high.
30	DVDD	power_in	1.8V supply for the digital output drivers; bypass each DVDD pin to ground with a separate 0.1µF ceramic capacitor.
31	D10_11-	output	DDR LVDS data output, complementary: carries bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high.
32	D10_11+	output	DDR LVDS data output: carries bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high.
33	D12_13-	output	DDR LVDS data output, complementary: carries bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high.
34	D12_13+	output	DDR LVDS data output: carries bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high.
35	GND	power_in	Power ground; the exposed pad on the back must be soldered to the PCB ground.
36	SPI_MISO	output	SPI data output in serial mode (MODE=0); open-drain, requires a 2kΩ pull-up to the 1.8V to 3.3V SPI supply when registers are read back, and has no effect in parallel mode.
37	SPI_MOSI	input	SPI data input in serial mode (MODE=0); in parallel mode (MODE=VDD) it selects the LVDS output current, 3.5mA when low and 1.75mA when high at 1.8V to 3.3V logic levels.
38	SPI_SCLK	input	SPI clock input in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables sleep mode when high at 1.8V to 3.3V logic levels.
39	SPI_CS	input	SPI chip select in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables the clock duty cycle stabilizer when high at 1.8V to 3.3V logic levels.
40	MODE	input	Serial/parallel mode select: tie to GND for SPI mode or to VDD for parallel GPIO mode; it must be hard-wired to GND or VDD and not driven by a logic signal.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Zynalog
Package	QFN-40(6x6)
Category	ADC/DAC/Data Conversion
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog supply voltage VDD	VDD	1.7	1.8	1.9	V		4
Digital supply voltage DVDD	DVDD	1.7	1.8	1.9	V		4
Analog supply input current	I_VDD		170	172	mA		4
Digital supply input current	I_DVDD		41		mA		4
Power dissipation with 1.75mA LVDS output	P_1.75		338		mW	1.75mA LVDS output	4
Power dissipation with 3.5mA LVDS output	P_3.5		378		mW	3.5mA LVDS output	4
Power dissipation in low power mode	P_lowpower		104		mW		4
Power dissipation in sleep mode	P_sleep		0.65		mW		4
Integral nonlinearity	INL	-2	1	2	LSB		4
Differential nonlinearity	DNL	-0.6	0.35	0.6	LSB		4
Offset error	Offset Error	-13	5	13	mV		4
Gain error	Gain Error	-4	1	2.2	%FS		4
Signal-to-noise ratio	SNR		70		dB		4
Spurious-free dynamic range	SFDR		90		dB		4
Digital output differential voltage (3.5mA mode)	V_OD	247	350	454	mV	3.5mA mode	4
Digital output differential voltage (1.75mA mode)	V_OD	125	175	250	mV	1.75mA mode	4
Digital output common-mode voltage	V_OS	1.125	1.25	1.375	V		4
Clock input to data acquisition delay	tAP		1		ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Clock input high hold time	tH	1.9	2		ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Clock input low hold time	tL	1.9	2		ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Clock input to clock output delay	tC	1.3	1.6	2	ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Clock input to data output delay	tD	1.7	2	2.3	ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
Clock output to data output skew (tC - tD)	tSKEW	0.3	0.4	0.55	ns	VDD=1.8V, DVDD=1.8V, fS=250MHz	10
CS low to clock setup time	tS		5		ns	SPI_MISO pull-up 2KΩ	15
Data setup time	tDS		5		ns	SPI_MISO pull-up 2KΩ	15
Data hold time	tDH		5		ns	SPI_MISO pull-up 2KΩ	15
Clock to data output delay	tDO		125		ns	SPI_MISO pull-up 2KΩ	15
Clock period (write)	tSCK		40		ns	write; SPI_MISO pull-up 2KΩ	15
Clock period (readback)	tSCK		250		ns	readback; SPI_MISO pull-up 2KΩ	15
Clock to CS high hold time	tH		5		ns	SPI_MISO pull-up 2KΩ	15
VDD, DVDD maximum input voltage range	VDD,DVDD	-0.3		2	V		6
Maximum analog input voltage range (Analog Vin)	Analog Vin	-0.3			V	upper limit printed as VDD+0.2	6
Maximum analog input voltage range (CLK, SENSE)	CLK,SENSE	-0.3			V	upper limit printed as VDD+0.2	6
Maximum SPI/GPIO digital voltage range	SPI			3.9	V	lower limit printed as VDD	6
Maximum LVDS output digital voltage range	Data Output	-0.3			V	upper limit printed as DVDD+0.2	6
Working temperature	WORKING TEMP	-40		85	°C		6
Storage temperature	STORAGE TEMP	-65		150	°C		6

CAD (KiCad official)

Symbol: ZGAD250S14
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: QFN-40(6x6) (KiCad packages3D, STEP)
3D model files: zgad250s14-etched.step / zgad250s14-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); zgad250s14.step / zgad250s14.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Zynalog datasheet (19 pp, sha256 b85a16310fc2dd7b, retrieved 2026-11-02, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ZGAD250S14

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