ZGAD250S14

{
  "slug": "zgad250s14",
  "version": "0.1.0",
  "type": "component",
  "description": "Zynalog Analog To Digital Converters (ADCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "adc-dac-data conversion",
    "zgad250s14",
    "factory-2.0.0",
    "extractor-text"
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  "dependencies": {},
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    "zgad250s14.step",
    "zgad250s14.lbr",
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    "viewers/footprint.html",
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  "component": {
    "mpn": "ZGAD250S14",
    "manufacturer": "Zynalog",
    "package": "QFN-40(6x6)",
    "pin_count": 41,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Analog To Digital Converters (ADCs)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/d938c81ef207be9905ddf99aeaf21085.pdf",
    "parts": {
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      "lbr": "zgad250s14.lbr"
    },
    "distributor_links": {
      "lcsc": "C7527745"
    },
    "distributor_check": {
      "checked_at": "2026-11-02T17:47:44Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply input; bypass to ground with a 0.1µF ceramic capacitor, and pins 1 and 2 may share one bypass capacitor."
      },
      {
        "number": "2",
        "name": "VDD",
        "type": "power_in",
        "description": "1.8V analog supply input; bypass to ground with a 0.1µF ceramic capacitor, and pins 1 and 2 may share one bypass capacitor."
      },
      {
        "number": "3",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
      },
      {
        "number": "4",
        "name": "Vin+",
        "type": "power_in",
        "description": "Positive differential analog input; the differential input must stay within 1.5V and be driven 180° out of phase with Vin-, using the VCM common-mode voltage."
      },
      {
        "number": "5",
        "name": "Vin-",
        "type": "power_in",
        "description": "Negative differential analog input; the differential input must stay within 1.5V and be driven 180° out of phase with Vin+, using the VCM common-mode voltage."
      },
      {
        "number": "6",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
      },
      {
        "number": "7",
        "name": "SENSE",
        "type": "input",
        "description": "External reference input: tie to VDD to select the internal reference (±0.75V input range), or drive with an external reference between 1.2V and 1.3V (±0.6*VSENSE input range)."
      },
      {
        "number": "8",
        "name": "VREF",
        "type": "power_in",
        "description": "Reference voltage output, nominally 1.25V; bypass to ground with a 2.2µF ceramic capacitor."
      },
      {
        "number": "9",
        "name": "VCM",
        "type": "output",
        "description": "Common-mode bias output, nominally 0.435*VDD; use it to set the common-mode bias of the analog inputs and bypass to ground with a 0.1µF ceramic capacitor."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
      },
      {
        "number": "11",
        "name": "CLK+",
        "type": "input",
        "description": "Positive sampling clock input; conversion starts on the rising edge of the clock."
      },
      {
        "number": "12",
        "name": "CLK-",
        "type": "input",
        "description": "Negative sampling clock input; conversion starts on the falling edge of the clock."
      },
      {
        "number": "13",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
      },
      {
        "number": "14",
        "name": "OF-",
        "type": "output",
        "description": "Overflow/underflow LVDS output, complementary signal; OF+ is high when an overflow or underflow occurs."
      },
      {
        "number": "15",
        "name": "OF+",
        "type": "output",
        "description": "Overflow/underflow LVDS output; OF+ is high when an overflow or underflow occurs."
      },
      {
        "number": "16",
        "name": "D0_1-",
        "type": "output",
        "description": "DDR LVDS data output, complementary: carries bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
      },
      {
        "number": "17",
        "name": "D0_1+",
        "type": "output",
        "description": "DDR LVDS data output: carries bit D0 while CLKOUT+ is low and bit D1 while CLKOUT+ is high."
      },
      {
        "number": "18",
        "name": "D2_3-",
        "type": "output",
        "description": "DDR LVDS data output, complementary: carries bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
      },
      {
        "number": "19",
        "name": "D2_3+",
        "type": "output",
        "description": "DDR LVDS data output: carries bit D2 while CLKOUT+ is low and bit D3 while CLKOUT+ is high."
      },
      {
        "number": "20",
        "name": "DVDD",
        "type": "power_in",
        "description": "1.8V supply for the digital output drivers; bypass each DVDD pin to ground with a separate 0.1µF ceramic capacitor."
      },
      {
        "number": "21",
        "name": "DGND",
        "type": "power_in",
        "description": "Ground for the digital output drivers."
      },
      {
        "number": "22",
        "name": "D4_5-",
        "type": "output",
        "description": "DDR LVDS data output, complementary: carries bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
      },
      {
        "number": "23",
        "name": "D4_5+",
        "type": "output",
        "description": "DDR LVDS data output: carries bit D4 while CLKOUT+ is low and bit D5 while CLKOUT+ is high."
      },
      {
        "number": "24",
        "name": "D6_7-",
        "type": "output",
        "description": "DDR LVDS data output, complementary: carries bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
      },
      {
        "number": "25",
        "name": "D6_7+",
        "type": "output",
        "description": "DDR LVDS data output: carries bit D6 while CLKOUT+ is low and bit D7 while CLKOUT+ is high."
      },
      {
        "number": "26",
        "name": "CLKOUT-",
        "type": "output",
        "description": "Data output clock LVDS, complementary; normally switches together with the falling and rising edges of CLKOUT+."
      },
      {
        "number": "27",
        "name": "CLKOUT+",
        "type": "output",
        "description": "Data output clock LVDS; normally switches on the falling and rising edges of the data outputs, and its phase can be delayed relative to the data by register programming."
      },
      {
        "number": "28",
        "name": "D8_9-",
        "type": "output",
        "description": "DDR LVDS data output, complementary: carries bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
      },
      {
        "number": "29",
        "name": "D8_9+",
        "type": "output",
        "description": "DDR LVDS data output: carries bit D8 while CLKOUT+ is low and bit D9 while CLKOUT+ is high."
      },
      {
        "number": "30",
        "name": "DVDD",
        "type": "power_in",
        "description": "1.8V supply for the digital output drivers; bypass each DVDD pin to ground with a separate 0.1µF ceramic capacitor."
      },
      {
        "number": "31",
        "name": "D10_11-",
        "type": "output",
        "description": "DDR LVDS data output, complementary: carries bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
      },
      {
        "number": "32",
        "name": "D10_11+",
        "type": "output",
        "description": "DDR LVDS data output: carries bit D10 while CLKOUT+ is low and bit D11 while CLKOUT+ is high."
      },
      {
        "number": "33",
        "name": "D12_13-",
        "type": "output",
        "description": "DDR LVDS data output, complementary: carries bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
      },
      {
        "number": "34",
        "name": "D12_13+",
        "type": "output",
        "description": "DDR LVDS data output: carries bit D12 while CLKOUT+ is low and bit D13 while CLKOUT+ is high."
      },
      {
        "number": "35",
        "name": "GND",
        "type": "power_in",
        "description": "Power ground; the exposed pad on the back must be soldered to the PCB ground."
      },
      {
        "number": "36",
        "name": "SPI_MISO",
        "type": "output",
        "description": "SPI data output in serial mode (MODE=0); open-drain, requires a 2kΩ pull-up to the 1.8V to 3.3V SPI supply when registers are read back, and has no effect in parallel mode."
      },
      {
        "number": "37",
        "name": "SPI_MOSI",
        "type": "input",
        "description": "SPI data input in serial mode (MODE=0); in parallel mode (MODE=VDD) it selects the LVDS output current, 3.5mA when low and 1.75mA when high at 1.8V to 3.3V logic levels."
      },
      {
        "number": "38",
        "name": "SPI_SCLK",
        "type": "input",
        "description": "SPI clock input in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables sleep mode when high at 1.8V to 3.3V logic levels."
      },
      {
        "number": "39",
        "name": "SPI_CS",
        "type": "input",
        "description": "SPI chip select in serial mode (MODE=0); in parallel mode (MODE=VDD) it enables the clock duty cycle stabilizer when high at 1.8V to 3.3V logic levels."
      },
      {
        "number": "40",
        "name": "MODE",
        "type": "input",
        "description": "Serial/parallel mode select: tie to GND for SPI mode or to VDD for parallel GPIO mode; it must be hard-wired to GND or VDD and not driven by a logic signal."
      },
      {
        "number": "41",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed thermal pad on the QFN40 package has no number and is not listed as a numbered pin. The "
        ],
        "pages_sent": 19,
        "cost_usd": 0.0445,
        "at": "2026-11-02T17:47:34"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/d938c81ef207be9905ddf99aeaf21085.pdf",
        "pages": 19,
        "sha256": "b85a16310fc2dd7b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 41,
        "described": 41,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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}