XL74LS10

{
  "slug": "xl74ls10",
  "version": "0.1.0",
  "type": "component",
  "description": "XINLUDA Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic ics",
    "xl74ls10",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "xl74ls10.kicad_sym",
    "xl74ls10.kicad_mod",
    "xl74ls10.glb",
    "xl74ls10.step",
    "xl74ls10.lbr",
    "docs/hero.png",
    "docs/xl74ls10-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "xl74ls10-hero.glb",
    "xl74ls10-hero.overlay.json",
    "xl74ls10-etched.glb"
  ],
  "component": {
    "mpn": "XL74LS10",
    "manufacturer": "XINLUDA",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic ICs",
    "subcategory": "Gates",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/dc514552de635bfeda35e4e551150865.pdf",
    "parts": {
      "symbol": "xl74ls10.kicad_sym",
      "footprint": "xl74ls10.kicad_mod",
      "model_3d": "xl74ls10-hero.glb",
      "model_3d_plain": "xl74ls10-etched.glb",
      "model_3d_step": "xl74ls10-etched.step",
      "model_3d_step_plain": "xl74ls10.step",
      "lbr": "xl74ls10.lbr"
    },
    "distributor_links": {
      "lcsc": "C521173"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T15:39:03Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Gate 1 input A; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Gate 1 input B; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "3",
        "name": "2A",
        "type": "input",
        "description": "Gate 2 input A; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "4",
        "name": "2B",
        "type": "input",
        "description": "Gate 2 input B; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "5",
        "name": "2C",
        "type": "input",
        "description": "Gate 2 input C; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Gate 2 NAND output; sources up to 0.4 mA high and sinks up to 8 mA low."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "8",
        "name": "3Y",
        "type": "output",
        "description": "Gate 3 NAND output; sources up to 0.4 mA high and sinks up to 8 mA low."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Gate 3 input A; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Gate 3 input B; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "11",
        "name": "3C",
        "type": "input",
        "description": "Gate 3 input C; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "12",
        "name": "1Y",
        "type": "output",
        "description": "Gate 1 NAND output; sources up to 0.4 mA high and sinks up to 8 mA low."
      },
      {
        "number": "13",
        "name": "1C",
        "type": "input",
        "description": "Gate 1 input C; high-level input voltage min 2 V, low-level max 0.8 V."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The description text says 'four independent 3-input NAND gates' but the title and pinout show three ",
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 5,
        "cost_usd": 0.2238,
        "at": "2026-10-30T15:38:20"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/dc514552de635bfeda35e4e551150865.pdf",
        "pages": 5,
        "sha256": "1a523ccd7ba973aa",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
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        "role": "plain",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "xl74ls10-etched.step",
        "role": "eda",
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        "units": "mm",
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  }
}