XL74LS08

{
  "schema_version": 1,
  "type": "component",
  "slug": "xl74ls08",
  "title": "XL74LS08",
  "brief": "XINLUDA Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "xl74ls08"
  ],
  "component": {
    "mpn": "XL74LS08",
    "manufacturer": "XINLUDA",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/34cf99fd2a534ec08e0ac6b8bcb72ec2.pdf",
    "parts": {
      "symbol": "xl74ls08.kicad_sym",
      "footprint": "xl74ls08.kicad_mod",
      "model_3d": "xl74ls08-etched.glb",
      "model_3d_plain": "xl74ls08.glb",
      "model_3d_step": "xl74ls08-etched.step",
      "model_3d_step_plain": "xl74ls08.step",
      "lbr": "xl74ls08.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Gate 1, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Gate 1, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Gate 1 output. Y = 1A AND 1B. IOH = -0.4 mA, IOL = 8 mA."
      },
      {
        "number": "4",
        "name": "2A",
        "type": "input",
        "description": "Gate 2, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "5",
        "name": "2B",
        "type": "input",
        "description": "Gate 2, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Gate 2 output. Y = 2A AND 2B. IOH = -0.4 mA, IOL = 8 mA."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V)."
      },
      {
        "number": "8",
        "name": "3Y",
        "type": "output",
        "description": "Gate 3 output. Y = 3A AND 3B. IOH = -0.4 mA, IOL = 8 mA."
      },
      {
        "number": "9",
        "name": "3A",
        "type": "input",
        "description": "Gate 3, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "10",
        "name": "3B",
        "type": "input",
        "description": "Gate 3, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Gate 4 output. Y = 4A AND 4B. IOH = -0.4 mA, IOL = 8 mA."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Gate 4, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Gate 4, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. Recommended 4.75-5.25 V (5 V nominal), absolute max 7 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/34cf99fd2a534ec08e0ac6b8bcb72ec2.pdf",
        "pages": 5,
        "sha256": "e46ba5a1c45d414d",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74LS08",
      "logic_family": "74LS",
      "function_code": "08",
      "function_class": "Gate",
      "function_name": "Quad 2-Input AND Gate",
      "manufacturer": "XL Semiconductor",
      "is_specialty": false
    }
  },
  "metadata": {
    "specs": {
      "Manufacturer": "XINLUDA",
      "Package": "SOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [
    {
      "mpn": "XL74LS08",
      "kind": "packaging"
    },
    {
      "mpn": "XL74LS08XD74LS08",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "xl74ls08"
  ],
  "discovery_pitch": "XL74LS08 (XINLUDA) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "xl74ls08.kicad_sym",
    "xl74ls08.kicad_mod",
    "xl74ls08.glb",
    "xl74ls08.step",
    "xl74ls08.lbr",
    "docs/hero.png",
    "docs/xl74ls08-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-25T14:37:02.852Z"
}