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XL74LS08

Public Made by Adom

by adom

XINLUDA Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs xl74ls08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
viewers xl74ls08: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md xl74ls08: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 13d ago
xl74ls08-etched.fit.json xl74ls08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
xl74ls08-etched.glb xl74ls08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
xl74ls08-etched.step xl74ls08: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 2d ago
xl74ls08.glb Publish 0.1.0 · Ray 1mo ago
xl74ls08.kicad_mod Publish 0.1.0 · Ray 1mo ago
xl74ls08.kicad_sym Publish 0.1.0 · Ray 1mo ago
xl74ls08.lbr Publish 0.1.0 · Ray 1mo ago
xl74ls08.step Publish 0.1.0 · Ray 1mo ago

XL74LS08

XINLUDA · Gates · SOP-14

XL74LS08 from XINLUDA, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
2 1B input Gate 1, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
3 1Y output Gate 1 output. Y = 1A AND 1B. IOH = -0.4 mA, IOL = 8 mA.
4 2A input Gate 2, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
5 2B input Gate 2, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
6 2Y output Gate 2 output. Y = 2A AND 2B. IOH = -0.4 mA, IOL = 8 mA.
7 GND power_in Ground reference (0 V).
8 3Y output Gate 3 output. Y = 3A AND 3B. IOH = -0.4 mA, IOL = 8 mA.
9 3A input Gate 3, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
10 3B input Gate 3, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
11 4Y output Gate 4 output. Y = 4A AND 4B. IOH = -0.4 mA, IOL = 8 mA.
12 4A input Gate 4, input A. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
13 4B input Gate 4, input B. TTL-compatible logic input (VIH ≥ 2 V, VIL ≤ 0.8 V).
14 VCC power_in Positive supply voltage. Recommended 4.75-5.25 V (5 V nominal), absolute max 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • XL74LS08
  • XL74LS08XD74LS08

CAD (KiCad official)

  • Symbol: XL74LS08
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: xl74ls08-etched.step / xl74ls08-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl74ls08.step / xl74ls08.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 e46ba5a1c45d414d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF