XL74HC595

{
  "schema_version": 1,
  "type": "component",
  "slug": "xl74hc595",
  "title": "XL74HC595",
  "brief": "XINLUDA Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "xl74hc595"
  ],
  "component": {
    "mpn": "XL74HC595",
    "manufacturer": "XINLUDA",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403181700_XINLUDA-XL74HC595_C2927048.pdf",
    "parts": {
      "symbol": "xl74hc595.kicad_sym",
      "footprint": "xl74hc595.kicad_mod",
      "model_3d": "xl74hc595-etched.glb",
      "model_3d_plain": "xl74hc595.glb",
      "model_3d_step": "xl74hc595-etched.step",
      "model_3d_step_plain": "xl74hc595.step",
      "lbr": "xl74hc595.lbr"
    },
    "distributor_links": {
      "lcsc": "C2927048"
    },
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Parallel tri-state output bit B from the 8-bit storage register. Drives up to -6 mA / +6 mA at VCC=4.5V and -7.8 mA / +7.8 mA at VCC=6V."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Parallel tri-state output bit C from the 8-bit storage register. Enabled when G is low."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Parallel tri-state output bit D from the 8-bit storage register. Enabled when G is low."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Parallel tri-state output bit E from the 8-bit storage register. Enabled when G is low."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Parallel tri-state output bit F from the 8-bit storage register. Enabled when G is low."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Parallel tri-state output bit G from the 8-bit storage register. Enabled when G is low."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Parallel tri-state output bit H (MSB) from the 8-bit storage register. Enabled when G is low."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Digital ground reference (0 V)."
      },
      {
        "number": "9",
        "name": "Q'H",
        "type": "output",
        "description": "Serial data output from the shift register (not tri-stated). Used for cascading multiple XL74HC595 devices; connect to SER of the next stage."
      },
      {
        "number": "10",
        "name": "SCLR",
        "type": "input",
        "description": "Shift register clear, active low. When low, the shift register contents are cleared (Q'H = 0). Does not affect the storage register."
      },
      {
        "number": "11",
        "name": "SCK",
        "type": "input",
        "description": "Shift register clock input. Rising edge shifts data from SER into the shift register. Max 30 MHz typical (VCC=6V, up to 108 MHz typ per AC characteristics)."
      },
      {
        "number": "12",
        "name": "RCK",
        "type": "input",
        "description": "Storage register (latch) clock input. Rising edge latches the current shift register contents into the 8-bit storage register, updating QA-QH."
      },
      {
        "number": "13",
        "name": "G",
        "type": "input",
        "description": "Output Enable, active low. When low, QA-QH are driven from the storage register; when high, QA-QH are in high-impedance state. Does not affect Q'H."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input. Value present at SER is shifted into the shift register on the rising edge of SCK."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Parallel tri-state output bit A (LSB) from the 8-bit storage register. Enabled when G is low."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Digital power supply, 2 V to 6 V (absolute max +7 V). Bypass with a 100 nF ceramic capacitor close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403181700_XINLUDA-XL74HC595_C2927048.pdf",
        "pages": 13,
        "sha256": "e0ba2b7daef7908f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC595",
      "logic_family": "74HC",
      "function_code": "595",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit SIPO Shift Register with Output Latch",
      "manufacturer": "XL Semiconductor",
      "is_specialty": false
    },
    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
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        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
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        "sha256": "3df9d0357101f65383d89195bb9d9c766ff8be9e8f17d82eff9168761c43d57c",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "XINLUDA",
      "Package": "SOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "xl74hc595"
  ],
  "discovery_pitch": "XL74HC595 (XINLUDA) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
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  "files": [
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    "README.md",
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    "xl74hc595.kicad_mod",
    "xl74hc595.glb",
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    "xl74hc595.lbr",
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    "docs/xl74hc595-datasheet.pdf",
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    "viewers/footprint.html",
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  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "XL74HC595",
      "kind": "packaging"
    },
    {
      "mpn": "XL74HC595TS",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T14:36:36.399Z"
}