component
XL7026E1
Public Made by Adomby adom
XLSEMI DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
Regenerate .lbr with adom-lbr 2.23.0: pin lengths map to the nearest EAGLE stop (overlapping pins fixed), unnamed pins take the pad number instead of ~ and ~@2, symbol body graphics are preserved, descriptions on the symbol, deviceset and package rows, and the package takes the footprint's own name so variants of one part share one footprint. Verified with lint and validate.
1 file changed
+6−5
xl7026e1.lbr+6−5@@ -50,10 +50,10 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description></description>+<description>XLSEMI DC-DC Converters, SOP-8-EP</description> <packages>-<package name="XL7026E1">- <description>XL7026E1</description>+<package name="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm">+ <description>SOIC-8-1EP, 3.9 x 4.9 mm, 1.27 mm pitch</description> <smd name="1" x="-2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/> <smd name="2" x="-2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="3" x="-2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/>@@ -87,6 +87,7 @@ </packages> <symbols> <symbol name="XL7026E1">+ <description>XLSEMI DC-DC Converters, SOP-8-EP</description> <wire x1="-12.7" y1="7.62" x2="12.7" y2="7.62" width="0.254" layer="94"/> <wire x1="12.7" y1="7.62" x2="12.7" y2="-7.62" width="0.254" layer="94"/> <wire x1="12.7" y1="-7.62" x2="-12.7" y2="-7.62" width="0.254" layer="94"/>@@ -106,12 +107,12 @@ </symbols> <devicesets> <deviceset name="XL7026E1" prefix="U">- <description></description>+ <description>XLSEMI DC-DC Converters, SOP-8-EP</description> <gates> <gate name="G$1" symbol="XL7026E1" x="0" y="0"/> </gates> <devices>- <device name="" package="XL7026E1">+ <device name="" package="SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm"> <connects> <connect gate="G$1" pin="FB" pad="1"/> <connect gate="G$1" pin="VREG" pad="2"/>