component
XL7026E1
Public Made by Adomby adom
XLSEMI DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
footprint: the shipped SOIC-8 has no thermal pad, but the symbol and the datasheet both show 9 pads. datasheet EP 2.29x3.1mm, nearest land 2.29x3.0mm (delta 0.10mm). Chosen from this part's OWN datasheet, not inferred from a sibling - the Richtek SOP-8-EP parts alone carry three different exposed-pad sizes, so family inference would have been wrong. Rebuilds the .lbr, re-derives pin 1 and pads.json.
3 files changed
+423−351
pads.json+40−20@@ -1,9 +1,9 @@ { "schema": "adom.pads/1", "slug": "xl7026e1",- "footprint": "SOIC-8_3.9x4.9mm_P1.27mm",+ "footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm", "generated_from": {- "footprint": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",+ "footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm@sha256:a7971720bdda0353", "pins": "page.json:component.pins", "overrides": null },@@ -15,9 +15,9 @@ ], "corner": "top-left", "source": "silk-marker",- "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4"+ "derived_from": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm@sha256:a7971720bdda0353" },- "pad_count": 8,+ "pad_count": 9, "symbol_pins": [ "1", "2",@@ -29,14 +29,8 @@ "8", "9" ],- "paste_apertures": 0,- "issues": [- {- "kind": "pin-has-no-pad",- "pin": "9",- "detail": "the symbol declares pin \"9\" but the footprint has no such pad"- }- ],+ "paste_apertures": 4,+ "issues": [], "pads": [ { "pad": "1",@@ -63,7 +57,7 @@ "description": "Feedback pin. Sensed against the internal 1.25 V reference through an external resistor divider from VOUT to set the output voltage (VOUT = 1.25 * (1 + R2/R1)).", "is_pin1": true, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }@@ -93,7 +87,7 @@ "description": "Chip supply pin. Requires a 10 µF decoupling capacitor between VREG and GND to filter noise. An external 7-9 V bias can be applied to this pin to reduce internal power dissipation.", "is_pin1": false, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }@@ -123,7 +117,7 @@ "description": "Internal voltage-regulator bypass pin. Requires a 1 µF ceramic capacitor connected between VC and VIN.", "is_pin1": false, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }@@ -153,7 +147,7 @@ "description": "Main power input, DC 12-90 V (demo tested up to 84 V). Bypass to GND with an electrolytic capacitor placed close to the pin to suppress switching noise and inrush spikes.", "is_pin1": false, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }@@ -183,7 +177,7 @@ "description": "Power-switch output pin. Connects to the external inductor and freewheeling Schottky diode of the buck converter. Tied together with pin 6 for current handling.", "is_pin1": false, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }@@ -213,7 +207,7 @@ "description": "Power-switch output pin (paralleled with pin 5). Connects to the switching node of the buck converter.", "is_pin1": false, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }@@ -243,7 +237,7 @@ "description": "Power/output ground return for the internal power stage. Tie to the ground plane at the input capacitor return.", "is_pin1": false, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }@@ -273,7 +267,33 @@ "description": "Signal ground reference for the control circuitry.", "is_pin1": false, "source": {- "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "9",+ "kind": "smd",+ "shape": "rect",+ "at": [+ 0.0,+ 0.0+ ],+ "rot": 0.0,+ "size": [+ 2.29,+ 3.0+ ],+ "layers": [],+ "thermal": true,+ "pin": "9",+ "name": "EP",+ "type": "power_in",+ "description": "Exposed thermal pad on the bottom of the SOP8-EP package. Solder to the ground copper pour for heat sinking; connect to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod", "meaning": "page.json:component.pins", "correspondence": "kicad: symbol pin number == pad name" }
xl7026e1.kicad_mod+331−300@@ -1,300 +1,331 @@-(footprint "SOIC-8_3.9x4.9mm_P1.27mm"- (version 20260206)- (generator "kicad-footprint-generator")- (layer "F.Cu")- (descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf)")- (tags "SOIC SO")- (property "Reference" "REF**"- (at 0 -3.4 0)- (layer "F.SilkS")- (effects- (font- (size 1 1)- (thickness 0.15)- )- )- )- (property "Value" "SOIC-8_3.9x4.9mm_P1.27mm"- (at 0 3.4 0)- (layer "F.Fab")- (effects- (font- (size 1 1)- (thickness 0.15)- )- )- )- (property "KiLib_Generator" "package/gullwing"- (at 0 0 0)- (layer "F.SilkS")- (hide yes)- (effects- (font- (size 1 1)- (thickness 0.15)- )- )- )- (attr smd)- (duplicate_pad_numbers_are_jumpers no)- (fp_line- (start -2.06 -2.56)- (end 2.06 -2.56)- (stroke- (width 0.12)- (type solid)- )- (layer "F.SilkS")- )- (fp_line- (start -2.06 -2.465)- (end -2.06 -2.56)- (stroke- (width 0.12)- (type solid)- )- (layer "F.SilkS")- )- (fp_line- (start -2.06 2.56)- (end -2.06 2.465)- (stroke- (width 0.12)- (type solid)- )- (layer "F.SilkS")- )- (fp_line- (start 2.06 -2.56)- (end 2.06 -2.465)- (stroke- (width 0.12)- (type solid)- )- (layer "F.SilkS")- )- (fp_line- (start 2.06 2.465)- (end 2.06 2.56)- (stroke- (width 0.12)- (type solid)- )- (layer "F.SilkS")- )- (fp_line- (start 2.06 2.56)- (end -2.06 2.56)- (stroke- (width 0.12)- (type solid)- )- (layer "F.SilkS")- )- (fp_poly- (pts- (xy -2.6 -2.47)- (xy -2.84 -2.8)- (xy -2.36 -2.8)- )- (stroke- (width 0.12)- (type solid)- )- (fill yes)- (layer "F.SilkS")- )- (fp_line- (start -3.7 -2.46)- (end -2.2 -2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start -3.7 2.46)- (end -3.7 -2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start -2.2 -2.7)- (end 2.2 -2.7)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start -2.2 -2.46)- (end -2.2 -2.7)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start -2.2 2.46)- (end -3.7 2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start -2.2 2.7)- (end -2.2 2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start 2.2 -2.7)- (end 2.2 -2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start 2.2 -2.46)- (end 3.7 -2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start 2.2 2.46)- (end 2.2 2.7)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start 2.2 2.7)- (end -2.2 2.7)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start 3.7 -2.46)- (end 3.7 2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_line- (start 3.7 2.46)- (end 2.2 2.46)- (stroke- (width 0.05)- (type solid)- )- (layer "F.CrtYd")- )- (fp_poly- (pts- (xy -0.975 -2.45)- (xy 1.95 -2.45)- (xy 1.95 2.45)- (xy -1.95 2.45)- (xy -1.95 -1.475)- )- (stroke- (width 0.1)- (type solid)- )- (fill no)- (layer "F.Fab")- )- (fp_text user "${REFERENCE}"- (at 0 0 90)- (layer "F.Fab")- (effects- (font- (size 1 1)- (thickness 0.15)- )- )- )- (pad "1" smd roundrect- (at -2.475 -1.905)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (pad "2" smd roundrect- (at -2.475 -0.635)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (pad "3" smd roundrect- (at -2.475 0.635)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (pad "4" smd roundrect- (at -2.475 1.905)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (pad "5" smd roundrect- (at 2.475 1.905)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (pad "6" smd roundrect- (at 2.475 0.635)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (pad "7" smd roundrect- (at 2.475 -0.635)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (pad "8" smd roundrect- (at 2.475 -1.905)- (size 1.95 0.6)- (layers "F.Cu" "F.Mask" "F.Paste")- (roundrect_rratio 0.25)- )- (embedded_fonts no)- (model "${KICAD10_3DMODEL_DIR}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.step"- (offset- (xyz 0 0 0)- )- (scale- (xyz 1 1 1)- )- (rotate- (xyz 0 0 0)- )- )-)+(footprint "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm" + (version 20260206) + (generator "kicad-footprint-generator") + (layer "F.Cu") + (descr "SOIC, 8 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/ada4898-1_4898-2.pdf#page=29)") + (tags "SOIC SO") + (property "Reference" "REF**" + (at 0 -3.4 0) + (layer "F.SilkS") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm" + (at 0 3.4 0) + (layer "F.Fab") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "KiLib_Generator" "package/gullwing" + (at 0 0 0) + (layer "F.SilkS") + (hide yes) + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (attr smd) + (duplicate_pad_numbers_are_jumpers no) + (fp_line + (start -2.06 -2.56) + (end 2.06 -2.56) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + ) + (fp_line + (start -2.06 -2.465) + (end -2.06 -2.56) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + ) + (fp_line + (start -2.06 2.56) + (end -2.06 2.465) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + ) + (fp_line + (start 2.06 -2.56) + (end 2.06 -2.465) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + ) + (fp_line + (start 2.06 2.465) + (end 2.06 2.56) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + ) + (fp_line + (start 2.06 2.56) + (end -2.06 2.56) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + ) + (fp_poly + (pts + (xy -2.6 -2.47) + (xy -2.84 -2.8) + (xy -2.36 -2.8) + ) + (stroke + (width 0.12) + (type solid) + ) + (fill yes) + (layer "F.SilkS") + ) + (fp_line + (start -3.7 -2.46) + (end -2.2 -2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start -3.7 2.46) + (end -3.7 -2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start -2.2 -2.7) + (end 2.2 -2.7) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start -2.2 -2.46) + (end -2.2 -2.7) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start -2.2 2.46) + (end -3.7 2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start -2.2 2.7) + (end -2.2 2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start 2.2 -2.7) + (end 2.2 -2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start 2.2 -2.46) + (end 3.7 -2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start 2.2 2.46) + (end 2.2 2.7) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start 2.2 2.7) + (end -2.2 2.7) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start 3.7 -2.46) + (end 3.7 2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_line + (start 3.7 2.46) + (end 2.2 2.46) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + ) + (fp_poly + (pts + (xy -0.975 -2.45) + (xy 1.95 -2.45) + (xy 1.95 2.45) + (xy -1.95 2.45) + (xy -1.95 -1.475) + ) + (stroke + (width 0.1) + (type solid) + ) + (fill no) + (layer "F.Fab") + ) + (fp_text user "${REFERENCE}" + (at 0 0 90) + (layer "F.Fab") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "" smd roundrect + (at -0.57 -0.75) + (size 0.92 1.21) + (layers "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "" smd roundrect + (at -0.57 0.75) + (size 0.92 1.21) + (layers "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "" smd roundrect + (at 0.57 -0.75) + (size 0.92 1.21) + (layers "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "" smd roundrect + (at 0.57 0.75) + (size 0.92 1.21) + (layers "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "1" smd roundrect + (at -2.475 -1.905) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "2" smd roundrect + (at -2.475 -0.635) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "3" smd roundrect + (at -2.475 0.635) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "4" smd roundrect + (at -2.475 1.905) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "5" smd roundrect + (at 2.475 1.905) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "6" smd roundrect + (at 2.475 0.635) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "7" smd roundrect + (at 2.475 -0.635) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "8" smd roundrect + (at 2.475 -1.905) + (size 1.95 0.6) + (layers "F.Cu" "F.Mask" "F.Paste") + (roundrect_rratio 0.25) + ) + (pad "9" smd rect + (at 0 0) + (size 2.29 3) + (property pad_prop_heatsink) + (layers "F.Cu" "F.Mask") + (zone_connect 2) + ) + (embedded_fonts no) + (model "${KICAD10_3DMODEL_DIR}/Package_SO.3dshapes/SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.step" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) +)
xl7026e1.lbr+52−31@@ -50,10 +50,10 @@ <layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/> </layers> <library>-<description>SOIC-8_3.9x4.9mm_P1.27mm (symbol synthesized from footprint pads)</description>+<description></description> <packages>-<package name="SOIC-8_3.9x4.9mm_P1.27mm">- <description>SOIC-8_3.9x4.9mm_P1.27mm</description>+<package name="XL7026E1">+ <description>XL7026E1</description> <smd name="1" x="-2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/> <smd name="2" x="-2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="3" x="-2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/>@@ -62,6 +62,19 @@ <smd name="6" x="2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/> <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>+ <smd name="9" x="0.0000" y="-0.0000" dx="2.2900" dy="3.0000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-2.6000" y="2.4700"/>+ <vertex x="-2.8400" y="2.8000"/>+ <vertex x="-2.3600" y="2.8000"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.9750" y="2.4500"/>+ <vertex x="1.9500" y="2.4500"/>+ <vertex x="1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="-2.4500"/>+ <vertex x="-1.9500" y="1.4750"/>+ </polygon> <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/> <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -73,42 +86,50 @@ <!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package> </packages> <symbols>-<symbol name="SOIC-8_3.9x4.9mm_P1.27mm">- <wire x1="-7.62" y1="6.35" x2="7.62" y2="6.35" width="0.254" layer="94"/>- <wire x1="7.62" y1="6.35" x2="7.62" y2="-6.35" width="0.254" layer="94"/>- <wire x1="7.62" y1="-6.35" x2="-7.62" y2="-6.35" width="0.254" layer="94"/>- <wire x1="-7.62" y1="-6.35" x2="-7.62" y2="6.35" width="0.254" layer="94"/>- <text x="0" y="8.89" size="1.27" layer="95" align="bottom-center">>NAME</text>- <text x="0" y="-8.89" size="1.27" layer="96" align="top-center">>VALUE</text>- <pin name="1" x="-12.7" y="5.08" length="short" direction="pas"/>- <pin name="2" x="-12.7" y="2.54" length="short" direction="pas"/>- <pin name="3" x="-12.7" y="0" length="short" direction="pas"/>- <pin name="4" x="-12.7" y="-2.54" length="short" direction="pas"/>- <pin name="5" x="12.7" y="5.08" length="short" direction="pas" rot="R180"/>- <pin name="6" x="12.7" y="2.54" length="short" direction="pas" rot="R180"/>- <pin name="7" x="12.7" y="0" length="short" direction="pas" rot="R180"/>- <pin name="8" x="12.7" y="-2.54" length="short" direction="pas" rot="R180"/>+<symbol name="XL7026E1">+ <wire x1="-12.7" y1="7.62" x2="12.7" y2="7.62" width="0.254" layer="94"/>+ <wire x1="12.7" y1="7.62" x2="12.7" y2="-7.62" width="0.254" layer="94"/>+ <wire x1="12.7" y1="-7.62" x2="-12.7" y2="-7.62" width="0.254" layer="94"/>+ <wire x1="-12.7" y1="-7.62" x2="-12.7" y2="7.62" width="0.254" layer="94"/>+ <text x="0" y="10.16" size="1.27" layer="95" align="bottom-center">>NAME</text>+ <text x="0" y="-10.16" size="1.27" layer="96" align="top-center">>VALUE</text>+ <pin name="FB" x="-17.78" y="5.08" length="middle" direction="in"/>+ <pin name="VREG" x="-17.78" y="2.54" length="middle" direction="pwr"/>+ <pin name="VC" x="-17.78" y="0" length="middle" direction="pas"/>+ <pin name="VIN" x="-17.78" y="-2.54" length="middle" direction="pwr"/>+ <pin name="SW" x="-17.78" y="-5.08" length="middle" direction="out"/>+ <pin name="EP" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="GND" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/>+ <pin name="OGND" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="SW@2" x="17.78" y="-5.08" length="middle" direction="out" rot="R180"/> </symbol> </symbols> <devicesets>-<deviceset name="SOIC-8_3.9x4.9mm_P1.27mm" prefix="U">- <description>SOIC-8_3.9x4.9mm_P1.27mm (symbol synthesized from footprint pads)</description>+<deviceset name="XL7026E1" prefix="U">+ <description></description> <gates>- <gate name="G$1" symbol="SOIC-8_3.9x4.9mm_P1.27mm" x="0" y="0"/>+ <gate name="G$1" symbol="XL7026E1" x="0" y="0"/> </gates> <devices>- <device name="" package="SOIC-8_3.9x4.9mm_P1.27mm">+ <device name="" package="XL7026E1"> <connects>- <connect gate="G$1" pin="1" pad="1"/>- <connect gate="G$1" pin="2" pad="2"/>- <connect gate="G$1" pin="3" pad="3"/>- <connect gate="G$1" pin="4" pad="4"/>- <connect gate="G$1" pin="5" pad="5"/>- <connect gate="G$1" pin="6" pad="6"/>- <connect gate="G$1" pin="7" pad="7"/>- <connect gate="G$1" pin="8" pad="8"/>+ <connect gate="G$1" pin="FB" pad="1"/>+ <connect gate="G$1" pin="VREG" pad="2"/>+ <connect gate="G$1" pin="VC" pad="3"/>+ <connect gate="G$1" pin="VIN" pad="4"/>+ <connect gate="G$1" pin="SW" pad="5"/>+ <connect gate="G$1" pin="EP" pad="9"/>+ <connect gate="G$1" pin="GND" pad="8"/>+ <connect gate="G$1" pin="OGND" pad="7"/>+ <connect gate="G$1" pin="SW@2" pad="6"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="XL7026E1" constant="no"/>+ <attribute name="MANUFACTURER" value="XLSEMI" constant="no"/>+ <attribute name="LCSC_PN" value="C89529" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>