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XL5615

Public Made by Adom

by adom

XINLUDA Digital To Analog Converters (DAC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XL5615

XINLUDA · Digital To Analog Converters (DAC) · SOP-8

XL5615 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN input Serial data input; the digital inputs use Schmitt triggers, with VIH at least 2.4 V and VIL at most 0.8 V.
2 SCLK input Serial clock input, which should be held low while CS is high to minimize clock feedthrough.
3 CS input Chip select input, active low, with CS-high setup and hold times to SCLK specified in the timing table.
4 DOUT output Serial data output for daisy chaining, with VOH at least VDD-1 V at IO = -2 mA and VOL at most 0.4 V at IO = 2 mA.
5 AGND power_in Analog ground reference for the DAC.
6 REFIN input Buffered high-impedance reference input; Vref is specified from 2 V minimum to VDD-2 V maximum (2.048 V nominal).
7 OUT output DAC analog voltage output, with a range of 0 V to VDD-0.4 V at RL = 10 kΩ.
8 VDD power_in Positive power supply, 4.5 V minimum, 5 V nominal, 5.5 V maximum.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-8
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VDD to AGND) 7 V 3
Digital input voltage range to AGND -0.3 V 3
Reference input voltage range to AGND -0.3 V 3
Continuous current at any terminal 20 mA 3
Operating free-air temperature range, TA (XL5615) TA -40 85 °C XL5615 3
Storage temperature range Tstg -65 150 °C 3
Lead temperature 260 °C 1.6 mm (1/16 inch) from case for 10 seconds 3
Supply voltage, VDD VDD 4.5 5 5.5 V 3
High-level digital input voltage VIH 2.4 V 3
Low-level digital input voltage VIL 0.8 V 3
Reference voltage, Vref to REFIN terminal Vref 2 2.048 V 3
Load resistance RL 2 kΩ 3
Operating free-air temperature, TA (XL5615) TA -40 85 °C XL5615 3
Integral nonlinearity, end point adjusted (INL) INL 1 LSB Vref = 2.048V, See (1) 3
Differential nonlinearity (DNL) DNL 0.1 0.5 LSB Vref = 2.048V, See (2) 3
Zero-scale error (offset error at zero scale) EZS 3 LSB Vref = 2.048V, See (3) 3
Zero-scale-error temperature coefficient 3 ppm/°C Vref = 2.048V, See (4) 3
Gain error EG 3 LSB Vref = 2.048V, See (5) 3
Gain-error temperature coefficient 1 ppm/°C Vref = 2.048V, See (6) 3
Power-supply rejection ratio, zero scale PSRR 80 dB Zero scale, See (7)(8) 3
Power-supply rejection ratio, gain PSRR 80 dB Gain 3
Voltage output range VO 0 V RL = 10k 4
Output load regulation accuracy 0.5 LSB VO(OUT) = 2V, RL = 2k 4
Output voltage, low-level VOL(low) 0.25 V IO(OUT) 5mA 4
Output voltage, high-level VOH(high) 4.75 V IO(OUT) -5mA 4
Reference input voltage VI 0 V 4
High-level digital input voltage (DIN, SCLK, CS) VIH 2.4 V 4
Low-level digital input voltage (DIN, SCLK, CS) VIL 0.8 V 4
High-level digital input current IIH 1 µA VI = VDD 4
Low-level digital input current IIL 1 µA VI = 0 4
Output voltage, low-level (DOUT) VOL 0.4 V IO = 2mA 4
Supply voltage (power supply table) VDD 4.5 5 5.5 V 4
Power supply current IDD 150 250 µA VDD = 5.5V, No load, All inputs = 0V or VDD, Vref = 0 4
Power supply current IDD 230 350 µA VDD = 5.5V, No load, All inputs = 0V or VDD, Vref = 2.048V 4
Signal-to-noise + distortion, S/(N+D) S/(N+D) 60 dB Vref = 1VPP at 1kHz + 2.048Vdc, code = 11 1111 1111 4
Setup time, DIN before SCLK high tsu(DS) 45 ns 4
Hold time, DIN valid after SCLK high th(DH) 0 ns 4
Setup time, CS low to SCLK high tsu(CSS) 1 ns 4
Setup time, CS high to SCLK high tsu(CS1) 50 ns 4
Hold time, SCLK low to CS low th(CSH0) 1 ns 4
Hold time, SCLK low to CS high th(CSH1) 0 ns 4
Minimum chip select pulse width high tw(CS) 20 ns 4
Pulse duration, SCLK low tw(CL) 25 ns 4
Pulse duration, SCLK high tw(CH) 25 ns 4
Propagation delay time, DOUT tpd(DOUT) 50 ns CL = 50pF 4
Output slew rate SR 0.3 0.5 V/s CL = 100pF, TA = +25C, RL = 10k 5
Low power consumption 1.75 mW 1

CAD (KiCad official)

  • Symbol: XL5615
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: xl5615-etched.step / xl5615-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl5615.step / xl5615.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (10 pp, sha256 7a9d2ee1c65d2060, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF