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XL549

Public Made by Adom

by adom

XINLUDA Analog To Digital Converters (ADC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XL549

XINLUDA · Analog To Digital Converters (ADC) · SOP-8

XL549 from XINLUDA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF+ input Positive reference voltage input, which must be kept within 2.5 V ≤ REF+ ≤ Vcc + 0.1 as printed.
2 ANALOG IN input Analog signal input sampled by the on-chip sample-and-hold, which starts sampling at the falling edge of the 4th I/O CLOCK and takes 4 I/O clock cycles for channel acquisition.
3 REF- input Negative reference voltage input, which must be kept within -0.1 V ≤ REF- ≤ 2.5 V.
4 GND power_in Ground reference for the device; the datasheet gives no further limits for this pin.
5 CS input Chip select input, which must be taken low to start a conversion sequence and must be high (or I/O CLOCK held low for 36 internal clock cycles) to complete the conversion.
6 DATA OUT output Serial conversion result output, which first presents the MSB (D7) on CS falling edge and then updates on I/O CLOCK falling edges, with output data remaining valid for at least 10 ns after I/O CLOCK falls.
7 I/O CLOCK input External clock input that drives the serial conversion timing; the on-chip 4 MHz system clock runs independently of it.
8 VCC power_in Supply voltage input with an operating range of 3 V to 6.5 V per the features list and a 6.5 V absolute maximum.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package SOP-8
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VCC VCC 3 5 6 V 3
High-level output voltage VOH 2.4 V VCC=4.75V 3
Low-level output voltage VOL 0.4 V VCC=4.75V 3
High-impedance off-state output current IOZ 10 μA VO=VCC 3
High-impedance off-state output current IOZ -10 μA VO=0 3
High-level input current, control inputs IIH 0.005 2.5 μA VI=VCC 3
Low-level input current, control inputs IIL -2.5 -0.005 μA VI=0 3
Analog channel on-state input current during sample cycle II(on) 0.4 μA Analog input at VCC 3
Analog channel on-state input current during sample cycle II(on) -1 1.8 μA Analog input at 0 V 3
Operating supply current ICC 1.9 3 mA CS at 0V 3
Full-scale error (EL row) EL -0.5 0.5 LSB 3
Zero-scale error (EZS row) EZS -0.5 0.5 LSB 3
Conversion time (label printed on EFS row) EFS -0.5 0.5 LSB 3
Conversion time tconv 12 17 μA 3
Total access and conversion time ta 19 25 μA 3
Channel acquisition time (sample cycle) 4 I/O clock cycles 3
Time output data remains valid after I/O CLOCK falling edge tv 10 ns 3
Time output data output valid td 400 ns 3
Output enable time ten 1.4 μA 3
Data bus fall time tdis 150 ns 3
Bus rise time (name not printed) tr(bus) 300 ns 3
Bus fall time (name not printed) Tf(bus) 300 ns 3
Supply voltage, VCC VCC 6.5 V 3
Input voltage range at any input -0.3 V Upper limit printed as VCC + 0.3 V 3
Output voltage range -0.3 V Upper limit printed as VCC + 0.3 V 3
Peak input current range (any input) -10 10 mA 3
Peak total input current range (all inputs) -30 30 mA 3
Operating free-air temperature range TA -20 85 °C 3
Storage temperature range Tstg -65 150 °C 3
Lead temperature 260 °C 1.6 mm (1/16 inch) from case for 10 seconds 3
Wide operating voltage (Features) VCC 3 6.5 V 1
Positive reference voltage input REF+ 2.5 V 2.5V≤REF+≤Vcc+0.1 (upper bound printed as Vcc+0.1) 2
Negative reference voltage input REF- -0.1 2.5 V -0.1V≤REF-≤2.5V 2
Differential reference voltage VREF+-VREF- 1 V 1

CAD (KiCad official)

  • Symbol: XL549
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: xl549-etched.step / xl549-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xl549.step / xl549.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (6 pp, sha256 d69dd73a48dd13c1, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF