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XD74LS181

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XINLUDA Specialty Logic, DIP-24. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs xd74ls181: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
viewers xd74ls181: viewers · Ray 26d ago
package.json Publish 0.1.0 · Ray 26d ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md xd74ls181: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
xd74ls181-etched.fit.json xd74ls181: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
xd74ls181-etched.glb xd74ls181: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
xd74ls181-etched.step xd74ls181: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 4d ago
xd74ls181.glb Publish 0.1.0 · Ray 26d ago
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xd74ls181.step Publish 0.1.0 · Ray 26d ago

XD74LS181

XINLUDA · Specialty Logic · DIP-24

XD74LS181 from XINLUDA, in a DIP-24. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 B0 input B-operand bit 0 input (active-low B0 for Table 1 / active-high B0 for Table 2). One of the four bits of the B operand presented to the ALU.
2 A0 input A-operand bit 0 input (active-low A0 for Table 1 / active-high A0 for Table 2). One of the four bits of the A operand presented to the ALU.
3 S3 input Function-select input bit 3. Together with S0-S2 selects one of 16 arithmetic or logic operations per Tables 1 and 2.
4 S2 input Function-select input bit 2. Together with S0, S1, S3 selects one of 16 ALU operations.
5 S1 input Function-select input bit 1. Together with S0, S2, S3 selects one of 16 ALU operations.
6 S0 input Function-select input bit 0. Together with S1, S2, S3 selects one of 16 ALU operations.
7 Cn input Carry input to the ALU (active-low Cn for Table 1 / active-high Cn for Table 2). Provides the incoming carry for arithmetic operations; ignored during logic operations when M is high.
8 M input Mode control input. M=H selects the 16 logic functions (internal carry disabled); M=L selects the 16 arithmetic operations (internal carries enabled).
9 F0 output Function output bit 0 (active-low F0 for Table 1 / active-high F0 for Table 2). Represents bit 0 of the ALU result F.
10 F1 output Function output bit 1 (active-low F1 for Table 1 / active-high F1 for Table 2). Represents bit 1 of the ALU result F.
11 F2 output Function output bit 2 (active-low F2 for Table 1 / active-high F2 for Table 2). Represents bit 2 of the ALU result F.
12 GND power_in Ground reference (0 V) for the device.
13 F3 output Function output bit 3 (active-low F3 for Table 1 / active-high F3 for Table 2). Represents the most-significant bit of the ALU result F.
14 A=B output Comparator output. Open-collector; goes high when the four F outputs are all high, indicating A equals B when the ALU is in subtract mode with Cn=H. Can be wire-AND'd across cascaded devices for comparison of more than four bits.
15 P output Carry propagate output (active-low P for Table 1 / X for Table 2). Used with a look-ahead carry generator such as the SN74LS182 to build fast wider adders.
16 Cn+4 output Ripple carry output from the ALU (active-low Cn+4 for Table 1 / active-high Cn+4 for Table 2). Provides the carry to the next 4-bit slice when full look-ahead is not used.
17 G output Carry generate output (active-low G for Table 1 / Y for Table 2). Combined with P and a look-ahead carry generator to produce fast carries for wider adders.
18 B3 input B-operand bit 3 (MSB) input (active-low B3 for Table 1 / active-high B3 for Table 2).
19 A3 input A-operand bit 3 (MSB) input (active-low A3 for Table 1 / active-high A3 for Table 2).
20 B2 input B-operand bit 2 input (active-low B2 for Table 1 / active-high B2 for Table 2).
21 A2 input A-operand bit 2 input (active-low A2 for Table 1 / active-high A2 for Table 2).
22 B1 input B-operand bit 1 input (active-low B1 for Table 1 / active-high B1 for Table 2).
23 A1 input A-operand bit 1 input (active-low A1 for Table 1 / active-high A1 for Table 2).
24 VCC power_in Supply voltage input. Recommended 4.75 V to 5.25 V (nominal 5 V); absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-24
Category Logic
Pins 24

CAD (KiCad official)

  • Symbol: XD74LS181
  • Footprint: Package_DIP:DIP-24_W7.62mm
  • 3D model: DIP-24 (KiCad packages3D, STEP)
  • 3D model files: xd74ls181-etched.step / xd74ls181-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls181.step / xd74ls181.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (11 pp, sha256 ab5b774bf827e79e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF