component
XD74LS10
Public Made by Adomby adom
XINLUDA Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518
{
"schema_version": 1,
"type": "component",
"slug": "xd74ls10",
"title": "XD74LS10",
"brief": "XINLUDA Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"logic",
"xd74ls10",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "XD74LS10",
"manufacturer": "XINLUDA",
"package": "DIP-14",
"pin_count": 14,
"category": "Logic",
"subcategory": "Logic Gates",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588895489638453248",
"parts": {
"symbol": "xd74ls10.kicad_sym",
"footprint": "xd74ls10.kicad_mod",
"model_3d": "xd74ls10-hero.glb",
"model_3d_plain": "xd74ls10-etched.glb",
"model_3d_step": "xd74ls10-etched.step",
"model_3d_step_plain": "xd74ls10.step",
"lbr": "xd74ls10.lbr"
},
"distributor_links": {
"lcsc": "C521172"
},
"distributor_check": {
"checked_at": "2026-10-16T10:52:02Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "1A",
"type": "input",
"description": "Gate 1 input A; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "2",
"name": "1B",
"type": "input",
"description": "Gate 1 input B; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "3",
"name": "2A",
"type": "input",
"description": "Gate 2 input A; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "4",
"name": "2B",
"type": "input",
"description": "Gate 2 input B; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "5",
"name": "2C",
"type": "input",
"description": "Gate 2 input C; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "6",
"name": "2Y",
"type": "output",
"description": "Gate 2 NAND output, low only when 2A, 2B and 2C are all high; IOH −0.4 mA max, IOL 8 mA max."
},
{
"number": "7",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the device."
},
{
"number": "8",
"name": "3Y",
"type": "output",
"description": "Gate 3 NAND output, low only when 3A, 3B and 3C are all high; IOH −0.4 mA max, IOL 8 mA max."
},
{
"number": "9",
"name": "3A",
"type": "input",
"description": "Gate 3 input A; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "10",
"name": "3B",
"type": "input",
"description": "Gate 3 input B; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "11",
"name": "3C",
"type": "input",
"description": "Gate 3 input C; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "12",
"name": "1Y",
"type": "output",
"description": "Gate 1 NAND output, low only when 1A, 1B and 1C are all high; IOH −0.4 mA max, IOL 8 mA max."
},
{
"number": "13",
"name": "1C",
"type": "input",
"description": "Gate 1 input C; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V."
},
{
"number": "14",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text+vision",
"consensus_model": "claude-opus-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The description says 'four independent 3-input NAND gates', but the title, pin diagram and logic dia",
"vision extraction: provenance cannot be text-verified; needs consensus"
],
"pages_sent": 5,
"cost_usd": 0.1693,
"at": "2026-10-16T10:51:43"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588895489638453248",
"pages": 5,
"sha256": "1a523ccd7ba973aa",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 14,
"described": 14,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "xd74ls10.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "body on z = 0, through-hole leads below",
"extents_mm": [
7.874,
19.05,
6.98
],
"zmin_mm": -3.3,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "3dae072a95c64bee0d1e58be8e75383639f5017ab982de1749d05808a4eed058",
"checked": "2026-10-16",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "xd74ls10-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "body on z = 0, through-hole leads below",
"extents_mm": [
7.874,
19.05,
6.98
],
"zmin_mm": -3.3,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "6d99f9f0fa8965383196d336a6b54d178782d0c60ce3aae576567d10eac03214",
"checked": "2026-10-16",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "XINLUDA",
"Package": "DIP-14",
"Category": "Logic",
"Pins": "14"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "1a523ccd7ba973aa36c1742d69d3bad80ff685a64a2600404ce6cadcde0c53b3",
"rows": [
{
"name": "Supply voltage (recommended)",
"symbol": "VCC",
"kind": "recommended_operating",
"unit": "V",
"min": 4.75,
"typ": 5,
"max": 5.25,
"conditions": "",
"source_page": 3,
"source": "datasheet"
},
{
"name": "High-level input voltage",
"symbol": "VIH",
"kind": "recommended_operating",
"unit": "V",
"min": 2,
"typ": null,
"max": null,
"conditions": "",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Low-level input voltage",
"symbol": "VIL",
"kind": "recommended_operating",
"unit": "V",
"min": null,
"typ": null,
"max": 0.8,
"conditions": "",
"source_page": 3,
"source": "datasheet"
},
{
"name": "High-level output current",
"symbol": "IOH",
"kind": "recommended_operating",
"unit": "mA",
"min": null,
"typ": null,
"max": -0.4,
"conditions": "",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Low-level output current",
"symbol": "IOL",
"kind": "recommended_operating",
"unit": "mA",
"min": null,
"typ": null,
"max": 8,
"conditions": "",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Operating free-air temperature (recommended)",
"symbol": "TA",
"kind": "recommended_operating",
"unit": "C",
"min": 0,
"typ": null,
"max": 70,
"conditions": "",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Supply voltage (absolute maximum)",
"symbol": "VCC",
"kind": "absolute_maximum",
"unit": "V",
"min": null,
"typ": null,
"max": 7,
"conditions": "see Note 1",
"source_page": 2,
"source": "datasheet"
},
{
"name": "Input voltage (74LS10)",
"symbol": "VI",
"kind": "absolute_maximum",
"unit": "V",
"min": null,
"typ": null,
"max": 7,
"conditions": "74LS10",
"source_page": 2,
"source": "datasheet"
},
{
"name": "Operating free-air temperature range (DIP package)",
"symbol": "",
"kind": "absolute_maximum",
"unit": "C",
"min": 0,
"typ": null,
"max": 70,
"conditions": "DIP package",
"source_page": 2,
"source": "datasheet"
},
{
"name": "Storage temperature range",
"symbol": "Tstg",
"kind": "absolute_maximum",
"unit": "C",
"min": -65,
"typ": null,
"max": 150,
"conditions": "",
"source_page": 2,
"source": "datasheet"
},
{
"name": "Input clamp voltage",
"symbol": "VIK",
"kind": "electrical",
"unit": "V",
"min": null,
"typ": null,
"max": -1.5,
"conditions": "VCC = MIN, II = −18 mA",
"source_page": 3,
"source": "datasheet"
},
{
"name": "High-level output voltage",
"symbol": "VOH",
"kind": "electrical",
"unit": "V",
"min": 2.7,
"typ": 3.4,
"max": null,
"conditions": "VCC = MIN, VIL = MAX, IOH = −0.4 mA",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Low-level output voltage",
"symbol": "VOL",
"kind": "electrical",
"unit": "V",
"min": null,
"typ": null,
"max": 0.4,
"conditions": "VCC = MIN, VIH = 2 V, IOL = 4 mA",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Low-level output voltage",
"symbol": "VOL",
"kind": "electrical",
"unit": "V",
"min": null,
"typ": 0.35,
"max": 0.5,
"conditions": "VCC = MIN, VIH = 2 V, IOL = 8 mA",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Maximum input current",
"symbol": "II",
"kind": "electrical",
"unit": "mA",
"min": null,
"typ": null,
"max": 0.1,
"conditions": "VCC = MAX, VI = 7 V",
"source_page": 3,
"source": "datasheet"
},
{
"name": "High-level input current",
"symbol": "IIH",
"kind": "electrical",
"unit": "A",
"min": null,
"typ": null,
"max": 20,
"conditions": "VCC = MAX, VI = 2.7 V",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Low-level input current",
"symbol": "IIL",
"kind": "electrical",
"unit": "mA",
"min": null,
"typ": null,
"max": -0.4,
"conditions": "VCC = MAX, VI = 0.4 V",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Short-circuit output current",
"symbol": "IOS",
"kind": "electrical",
"unit": "mA",
"min": -20,
"typ": null,
"max": -100,
"conditions": "VCC = MAX",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Supply current, outputs high",
"symbol": "ICCH",
"kind": "electrical",
"unit": "mA",
"min": null,
"typ": 0.6,
"max": 1.2,
"conditions": "VCC = MAX, VI = 4.5 V",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Supply current, outputs low",
"symbol": "ICCL",
"kind": "electrical",
"unit": "mA",
"min": null,
"typ": 1.8,
"max": 3.3,
"conditions": "VCC = MAX, VI = 0 V",
"source_page": 3,
"source": "datasheet"
},
{
"name": "Propagation delay high-to-low (A or B to Y)",
"symbol": "tPHL",
"kind": "timing",
"unit": "ns",
"min": null,
"typ": 10,
"max": 15,
"conditions": "VCC = 5 V, TA = 25 C; RL = 2 kΩ, CL = 15 pF",
"source_page": 3,
"source": "datasheet"
}
]
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"xd74ls10"
],
"discovery_pitch": "XD74LS10 (XINLUDA) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"xd74ls10.kicad_sym",
"xd74ls10.kicad_mod",
"xd74ls10.glb",
"xd74ls10.step",
"xd74ls10.lbr",
"docs/hero.png",
"docs/xd74ls10-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"xd74ls10-hero.glb",
"xd74ls10-hero.overlay.json",
"xd74ls10-etched.glb"
],
"visibility": {
"public": true
}
}