component

XD74LS10

Public Made by Adom

by adom

XINLUDA Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicxd74ls10factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

XD74LS10

XINLUDA · Logic Gates · DIP-14

XD74LS10 from XINLUDA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
2 1B input Gate 1 input B; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
3 2A input Gate 2 input A; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
4 2B input Gate 2 input B; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
5 2C input Gate 2 input C; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
6 2Y output Gate 2 NAND output, low only when 2A, 2B and 2C are all high; IOH −0.4 mA max, IOL 8 mA max.
7 GND power_in Ground reference for the device.
8 3Y output Gate 3 NAND output, low only when 3A, 3B and 3C are all high; IOH −0.4 mA max, IOL 8 mA max.
9 3A input Gate 3 input A; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
10 3B input Gate 3 input B; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
11 3C input Gate 3 input C; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
12 1Y output Gate 1 NAND output, low only when 1A, 1B and 1C are all high; IOH −0.4 mA max, IOL 8 mA max.
13 1C input Gate 1 input C; high-level input voltage min 2 V, low-level max 0.8 V, absolute max 7 V.
14 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal), absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (recommended) VCC 4.75 5 5.25 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
High-level output current IOH -0.4 mA 3
Low-level output current IOL 8 mA 3
Operating free-air temperature (recommended) TA 0 70 C 3
Supply voltage (absolute maximum) VCC 7 V see Note 1 2
Input voltage (74LS10) VI 7 V 74LS10 2
Operating free-air temperature range (DIP package) 0 70 C DIP package 2
Storage temperature range Tstg -65 150 C 2
Input clamp voltage VIK -1.5 V VCC = MIN, II = −18 mA 3
High-level output voltage VOH 2.7 3.4 V VCC = MIN, VIL = MAX, IOH = −0.4 mA 3
Low-level output voltage VOL 0.4 V VCC = MIN, VIH = 2 V, IOL = 4 mA 3
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, IOL = 8 mA 3
Maximum input current II 0.1 mA VCC = MAX, VI = 7 V 3
High-level input current IIH 20 A VCC = MAX, VI = 2.7 V 3
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 3
Short-circuit output current IOS -20 -100 mA VCC = MAX 3
Supply current, outputs high ICCH 0.6 1.2 mA VCC = MAX, VI = 4.5 V 3
Supply current, outputs low ICCL 1.8 3.3 mA VCC = MAX, VI = 0 V 3
Propagation delay high-to-low (A or B to Y) tPHL 10 15 ns VCC = 5 V, TA = 25 C; RL = 2 kΩ, CL = 15 pF 3

CAD (KiCad official)

  • Symbol: XD74LS10
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: xd74ls10-etched.step / xd74ls10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd74ls10.step / xd74ls10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (5 pp, sha256 1a523ccd7ba973aa, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF