XD7135

{
  "slug": "xd7135",
  "version": "0.1.0",
  "type": "component",
  "description": "XINLUDA Interface - Specialized, DIP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "xd7135",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "xd7135.kicad_sym",
    "xd7135.kicad_mod",
    "xd7135.glb",
    "xd7135.step",
    "xd7135.lbr",
    "docs/hero.png",
    "docs/xd7135-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "xd7135-hero.glb",
    "xd7135-hero.overlay.json",
    "xd7135-etched.glb"
  ],
  "component": {
    "mpn": "XD7135",
    "manufacturer": "XINLUDA",
    "package": "DIP-28",
    "pin_count": 28,
    "category": "Interface",
    "subcategory": "Interface - Specialized",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897521627881472",
    "parts": {
      "symbol": "xd7135.kicad_sym",
      "footprint": "xd7135.kicad_mod",
      "model_3d": "xd7135-hero.glb",
      "model_3d_plain": "xd7135-etched.glb",
      "model_3d_step": "xd7135-etched.step",
      "model_3d_step_plain": "xd7135.step",
      "lbr": "xd7135.lbr"
    },
    "distributor_links": {
      "lcsc": "C521138"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T10:39:44Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VCC-",
        "type": "power_in",
        "description": "Negative supply, recommended -3 V to -8 V (nominal -5 V) with respect to ground."
      },
      {
        "number": "2",
        "name": "REF",
        "type": "input",
        "description": "Reference voltage input, positive with respect to analog common, with Vref of 1 V recommended."
      },
      {
        "number": "3",
        "name": "ANLG COMMON",
        "type": "passive",
        "description": "Analog common, connected to internal IN- during auto-zero, deintegrate and zero integrator phases, and tied to the IN- reference point when IN- is at a fixed voltage."
      },
      {
        "number": "4",
        "name": "INT OUT",
        "type": "passive",
        "description": "Integrator output where the integrating capacitor CINT connects (nominal 0.47 uF) and the rollover-correction diode cathode attaches."
      },
      {
        "number": "5",
        "name": "AUTO ZERO",
        "type": "passive",
        "description": "Auto-zero capacitor CAZ connection that compensates buffer, integrator and comparator offsets (typical 1 uF)."
      },
      {
        "number": "6",
        "name": "BUFF OUT",
        "type": "passive",
        "description": "Buffer amplifier output where the integrating resistor RINT connects, sized for a nominal 20 uA integrator current."
      },
      {
        "number": "7",
        "name": "Cref-",
        "type": "passive",
        "description": "Negative terminal of the external reference capacitor (typical 1 uF)."
      },
      {
        "number": "8",
        "name": "Cref+",
        "type": "passive",
        "description": "Positive terminal of the external reference capacitor (typical 1 uF)."
      },
      {
        "number": "9",
        "name": "IN-",
        "type": "input",
        "description": "Negative differential analog input, within VCC- +1 V to VCC+ -0.5 V, with input leakage typically 1 pA."
      },
      {
        "number": "10",
        "name": "IN+",
        "type": "input",
        "description": "Positive differential analog input, within VCC- +1 V to VCC+ -0.5 V, with input leakage typically 1 pA."
      },
      {
        "number": "11",
        "name": "VCC+",
        "type": "power_in",
        "description": "Positive supply, recommended 4 V to 6 V (nominal 5 V) with respect to ground."
      },
      {
        "number": "12",
        "name": "D5",
        "type": "output",
        "description": "Digit-drive output for the most significant digit (D5), high for 200 clock pulses in the scan sequence."
      },
      {
        "number": "13",
        "name": "B1",
        "type": "output",
        "description": "Multiplexed BCD output bit 1 (weight 1), TTL-compatible."
      },
      {
        "number": "14",
        "name": "B2",
        "type": "output",
        "description": "Multiplexed BCD output bit 2 (weight 2), TTL-compatible."
      },
      {
        "number": "15",
        "name": "B4",
        "type": "output",
        "description": "Multiplexed BCD output bit 4 (weight 4), TTL-compatible."
      },
      {
        "number": "16",
        "name": "B8",
        "type": "output",
        "description": "Multiplexed BCD output bit 8 (weight 8), TTL-compatible."
      },
      {
        "number": "17",
        "name": "D4",
        "type": "output",
        "description": "Digit-drive output D4, high for 200 clock pulses in the scan sequence."
      },
      {
        "number": "18",
        "name": "D3",
        "type": "output",
        "description": "Digit-drive output D3, high for 200 clock pulses in the scan sequence."
      },
      {
        "number": "19",
        "name": "D2",
        "type": "output",
        "description": "Digit-drive output D2, high for 200 clock pulses in the scan sequence."
      },
      {
        "number": "20",
        "name": "D1",
        "type": "output",
        "description": "Digit-drive output for the least significant digit (D1), high for 200 clock pulses in the scan sequence."
      },
      {
        "number": "21",
        "name": "BUSY",
        "type": "output",
        "description": "Goes high at the start of signal integrate and stays high until the first clock after zero crossing, or until the end of the cycle on over-range."
      },
      {
        "number": "22",
        "name": "CLK",
        "type": "input",
        "description": "Clock input with VIH min 2.8 V and VIL max 0.8 V, operating frequency up to 1.2 to 2 MHz."
      },
      {
        "number": "23",
        "name": "POLARITY",
        "type": "output",
        "description": "Polarity output, high for a positive input, updated at the start of each deintegrate phase and valid for all inputs including OVER RANGE."
      },
      {
        "number": "24",
        "name": "DGTL GND",
        "type": "power_in",
        "description": "Digital ground, which should not carry return currents to the analog ground line."
      },
      {
        "number": "25",
        "name": "RUN/HOLD",
        "type": "input",
        "description": "High or open runs continuous 40,002-clock measurement cycles, while low holds the reading after the current cycle until a positive pulse greater than 300 ns starts a new one."
      },
      {
        "number": "26",
        "name": "STROBE",
        "type": "output",
        "description": "Active-low pulse, 1/2 clock wide at the midpoint of each digit-drive pulse, that transfers BCD data to external latches, UARTs or microprocessors."
      },
      {
        "number": "27",
        "name": "OVER RANGE",
        "type": "output",
        "description": "Goes high after BUSY falls at the end of an over-range measurement cycle and goes low at the start of the next deintegrate phase."
      },
      {
        "number": "28",
        "name": "UNDER RANGE",
        "type": "output",
        "description": "Goes high at the end of BUSY when the result is at or below 9% (count of 1800) of full scale, and low at the start of the next signal integrate phase."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Datasheet section 9.2 calls STROBE an 'input', but the block diagram arrow and the description show ; The datasheet gives no pin types for the analog passive pins (ANLG COMMON, INT OUT, AUTO ZERO, BUFF ; The block diagram labels pin 10 'IN' and the pinout labels it IN+. Pin 10 is taken as IN+.",
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 12,
        "cost_usd": 0.2494,
        "at": "2026-10-18T10:38:07"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588897521627881472",
        "pages": 12,
        "sha256": "31e7ace85a17c431",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 28,
        "described": 28,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "xd7135.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
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        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "7bf4503e368ad9b7a3eddfa94bc8dee656da5d6921b677e17307b3d7f29177ab",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "xd7135-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
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        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "ea219169fee26f0867f340bd91d9fce5b06589d31cfb1f8b714d6e0c71de4253",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}