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XD7135

Public Made by Adom

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XINLUDA Interface - Specialized, DIP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XD7135

XINLUDA · Interface - Specialized · DIP-28

XD7135 from XINLUDA, in a DIP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC- power_in Negative supply, recommended -3 V to -8 V (nominal -5 V) with respect to ground.
2 REF input Reference voltage input, positive with respect to analog common, with Vref of 1 V recommended.
3 ANLG COMMON passive Analog common, connected to internal IN- during auto-zero, deintegrate and zero integrator phases, and tied to the IN- reference point when IN- is at a fixed voltage.
4 INT OUT passive Integrator output where the integrating capacitor CINT connects (nominal 0.47 uF) and the rollover-correction diode cathode attaches.
5 AUTO ZERO passive Auto-zero capacitor CAZ connection that compensates buffer, integrator and comparator offsets (typical 1 uF).
6 BUFF OUT passive Buffer amplifier output where the integrating resistor RINT connects, sized for a nominal 20 uA integrator current.
7 Cref- passive Negative terminal of the external reference capacitor (typical 1 uF).
8 Cref+ passive Positive terminal of the external reference capacitor (typical 1 uF).
9 IN- input Negative differential analog input, within VCC- +1 V to VCC+ -0.5 V, with input leakage typically 1 pA.
10 IN+ input Positive differential analog input, within VCC- +1 V to VCC+ -0.5 V, with input leakage typically 1 pA.
11 VCC+ power_in Positive supply, recommended 4 V to 6 V (nominal 5 V) with respect to ground.
12 D5 output Digit-drive output for the most significant digit (D5), high for 200 clock pulses in the scan sequence.
13 B1 output Multiplexed BCD output bit 1 (weight 1), TTL-compatible.
14 B2 output Multiplexed BCD output bit 2 (weight 2), TTL-compatible.
15 B4 output Multiplexed BCD output bit 4 (weight 4), TTL-compatible.
16 B8 output Multiplexed BCD output bit 8 (weight 8), TTL-compatible.
17 D4 output Digit-drive output D4, high for 200 clock pulses in the scan sequence.
18 D3 output Digit-drive output D3, high for 200 clock pulses in the scan sequence.
19 D2 output Digit-drive output D2, high for 200 clock pulses in the scan sequence.
20 D1 output Digit-drive output for the least significant digit (D1), high for 200 clock pulses in the scan sequence.
21 BUSY output Goes high at the start of signal integrate and stays high until the first clock after zero crossing, or until the end of the cycle on over-range.
22 CLK input Clock input with VIH min 2.8 V and VIL max 0.8 V, operating frequency up to 1.2 to 2 MHz.
23 POLARITY output Polarity output, high for a positive input, updated at the start of each deintegrate phase and valid for all inputs including OVER RANGE.
24 DGTL GND power_in Digital ground, which should not carry return currents to the analog ground line.
25 RUN/HOLD input High or open runs continuous 40,002-clock measurement cycles, while low holds the reading after the current cycle until a positive pulse greater than 300 ns starts a new one.
26 STROBE output Active-low pulse, 1/2 clock wide at the midpoint of each digit-drive pulse, that transfers BCD data to external latches, UARTs or microprocessors.
27 OVER RANGE output Goes high after BUSY falls at the end of an over-range measurement cycle and goes low at the start of the next deintegrate phase.
28 UNDER RANGE output Goes high at the end of BUSY when the result is at or below 9% (count of 1800) of full scale, and low at the start of the next signal integrate phase.

Key specifications

Parameter Value
Manufacturer XINLUDA
Package DIP-28
Category Interface
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VCC+ with respect to VCC−) 15 V 4
Storage temperature range, Tstg Tstg -65 150 °C 4
Operating free-air temperature range, TA TA 0 70 °C 4
Lead temperature, N package 260 °C 1.6 mm (1/16 inch) from case for 10 seconds 4
Clock input voltage range 0 V 4
Supply voltage, VCC+ VCC+ 4 5 6 V 4
Supply voltage, VCC− VCC− -3 -5 -8 V 4
High-level input voltage, CLK, RUN/HOLD VIH 2.8 V 4
Low-level input voltage, CLK, RUN/HOLD VIL 0.8 V 4
Maximum operating frequency fclock 1.2 2 MHz see Note 1 4
Operating free-air temperature range, TA TA 0 70 °C 4
High-level output voltage, D1-D5, B1, B2, B4, B8 VOH 2.4 V IO = −1 mA 4
High-level output voltage, other outputs VOH 4.9 5 V IO = −10 µA 4
Low-level output voltage VOL 0.4 V IO = 1.6 mA 4
High-level input current IIH 0.1 10 µA VI = 5 V, 0°C ≤ TA ≤ 70°C 4
Low-level input current IIL -0.02 -0.1 mA VI = 0 V, 0°C ≤ TA ≤ 70°C 4
Input leakage current, IN− and IN+ II 1 10 pA VID = 0, TA = 25°C 4
Input leakage current, IN− and IN+ II 250 pA VID = 0, 0°C ≤ TA ≤ 70°C 4
Positive supply current ICC+ 1 2 mA fclock = 0, TA = 25°C 4
Positive supply current ICC+ 3 mA fclock = 0, 0°C ≤ TA ≤ 70°C 4
Negative supply current ICC− -0.8 -2 mA fclock = 0, TA = 25°C 4
Negative supply current ICC− -3 mA fclock = 0, 0°C ≤ TA ≤ 70°C 4
Digital reading with 0-V input (display reading) 0 0 0 Digital Reading VID = 0, 0°C ≤ TA ≤ 70°C 5
Display reading in ratiometric operation 0.9998 0.9999 1 Digital Reading VID = Vref, TA = 25°C 5
Display reading in ratiometric operation 0.9995 0.9999 1.0005 Digital Reading VID = Vref, 0°C ≤ TA ≤ 70°C 5
Zero-reading temperature coefficient of output voltage VO 0.5 2 µV/°C VID = 0, 0°C ≤ TA ≤ 70°C 4
Peak-to-peak output noise voltage VON(PP) 15 µV VID = 0, Full scale = 2 V; see Note 1 4
Full-scale temperature coefficient FS 5 ppm/°C VID = 2 V, 0°C ≤ TA ≤ 70°C; see Note 1 5
Linearity error EL 0.5 count −2 V ≤ VID ≤ 2 V 5
Differential linearity error ED 0.01 LSB −2 V ≤ VID ≤ 2 V; see Note 2 5
Full-scale symmetry error (rollover error) EFS 0.5 1 count VID = 2 V; see Note 3 5
Power dissipation capacitance Cpd 40 pF See Note 2 4

CAD (KiCad official)

  • Symbol: XD7135
  • Footprint: Package_DIP:DIP-28_W7.62mm
  • 3D model: DIP-28 (KiCad packages3D, STEP)
  • 3D model files: xd7135-etched.step / xd7135-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xd7135.step / xd7135.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XINLUDA datasheet (12 pp, sha256 31e7ace85a17c431, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF