XC3S250E-4VQG100I

{
  "slug": "xc3s250e-4vqg100i",
  "version": "0.1.0",
  "type": "component",
  "description": "XILINX Programmable Logic Device (CPLDs/FPGAs), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "xc3s250e-4vqg100i",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "xc3s250e-4vqg100i.kicad_sym",
    "xc3s250e-4vqg100i.kicad_mod",
    "xc3s250e-4vqg100i.glb",
    "xc3s250e-4vqg100i.step",
    "xc3s250e-4vqg100i.lbr",
    "docs/hero.png",
    "docs/xc3s250e-4vqg100i-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "xc3s250e-4vqg100i-hero.glb",
    "xc3s250e-4vqg100i-hero.overlay.json",
    "xc3s250e-4vqg100i-etched.glb"
  ],
  "component": {
    "mpn": "XC3S250E-4VQG100I",
    "manufacturer": "XILINX",
    "package": "QFP-100(14x14)",
    "pin_count": 100,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Programmable Logic Device (CPLDs/FPGAs)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/6dfdb8a51adc67c061be88553e165f26.pdf",
    "parts": {
      "symbol": "xc3s250e-4vqg100i.kicad_sym",
      "footprint": "xc3s250e-4vqg100i.kicad_mod",
      "model_3d": "xc3s250e-4vqg100i-hero.glb",
      "model_3d_plain": "xc3s250e-4vqg100i-etched.glb",
      "model_3d_step": "xc3s250e-4vqg100i-etched.step",
      "model_3d_step_plain": "xc3s250e-4vqg100i.step",
      "lbr": "xc3s250e-4vqg100i.lbr"
    },
    "distributor_links": {
      "lcsc": "C2684980",
      "digikey": "122-1715-ND",
      "mouser": "217-C3S250E-4VQG100I"
    },
    "distributor_check": {
      "checked_at": "2026-10-23T03:26:14Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "122-1715-ND",
        "status": "found",
        "lifecycle": "Obsolete"
      },
      "mouser": {
        "pn": "217-C3S250E-4VQG100I",
        "status": "found",
        "lifecycle": "Obsolete"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "PROG_B",
        "type": "input",
        "description": "Dedicated active-Low configuration pin (powered by VCCAUX) that restarts configuration when held Low for 500 ns or longer."
      },
      {
        "number": "2",
        "name": "IO_L01P_3",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, true side of differential pair L01."
      },
      {
        "number": "3",
        "name": "IO_L01N_3",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, inverted side of differential pair L01."
      },
      {
        "number": "4",
        "name": "IO_L02P_3",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, true side of differential pair L02."
      },
      {
        "number": "5",
        "name": "IO_L02N_3/VREF_3",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, inverted side of pair L02, or VREF input for bank 3 when an HSTL/SSTL standard is used."
      },
      {
        "number": "6",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply, +1.2V."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "8",
        "name": "VCCO_3",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 3 (all VCCO_3 pins must be connected)."
      },
      {
        "number": "9",
        "name": "IO_L03P_3/LHCLK0",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, true side of pair L03, or left-half clock input LHCLK0."
      },
      {
        "number": "10",
        "name": "IO_L03N_3/LHCLK1",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, inverted side of pair L03, or left-half clock input LHCLK1."
      },
      {
        "number": "11",
        "name": "IO_L04P_3/LHCLK2",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, true side of pair L04, or left-half clock input LHCLK2."
      },
      {
        "number": "12",
        "name": "IO_L04N_3/LHCLK3",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, inverted side of pair L04, or left-half clock input LHCLK3."
      },
      {
        "number": "13",
        "name": "IP",
        "type": "input",
        "description": "Unrestricted general-purpose input-only pin in bank 3."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "15",
        "name": "IO_L05P_3/LHCLK4",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, true side of pair L05, or left-half clock input LHCLK4."
      },
      {
        "number": "16",
        "name": "IO_L05N_3/LHCLK5",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, inverted side of pair L05, or left-half clock input LHCLK5."
      },
      {
        "number": "17",
        "name": "IO_L06P_3/LHCLK6",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, true side of pair L06, or left-half clock input LHCLK6."
      },
      {
        "number": "18",
        "name": "IO_L06N_3/LHCLK7",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, inverted side of pair L06, or left-half clock input LHCLK7."
      },
      {
        "number": "19",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "20",
        "name": "VCCO_3",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 3 (all VCCO_3 pins must be connected)."
      },
      {
        "number": "21",
        "name": "VCCAUX",
        "type": "power_in",
        "description": "Auxiliary supply, +2.5V."
      },
      {
        "number": "22",
        "name": "IO_L07P_3",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, true side of differential pair L07."
      },
      {
        "number": "23",
        "name": "IO_L07N_3",
        "type": "bidirectional",
        "description": "Bank 3 user I/O, inverted side of differential pair L07."
      },
      {
        "number": "24",
        "name": "IO_L01P_2/CSO_B",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin, true side of pair L01; CSO_B chip-select output during configuration, then user I/O."
      },
      {
        "number": "25",
        "name": "IO_L01N_2/INIT_B",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; open-drain active-Low initialization indicator during configuration, then user I/O."
      },
      {
        "number": "26",
        "name": "IO_L02P_2/DOUT/BUSY",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; DOUT/BUSY output during configuration, then user I/O."
      },
      {
        "number": "27",
        "name": "IO_L02N_2/MOSI/CSI_B",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; MOSI or CSI_B during configuration, then user I/O."
      },
      {
        "number": "28",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply, +1.2V."
      },
      {
        "number": "29",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "30",
        "name": "IP/VREF_2",
        "type": "input",
        "description": "Bank 2 input-only pin that also serves as VREF input for bank 2 when HSTL/SSTL is used."
      },
      {
        "number": "31",
        "name": "VCCO_2",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 2 (all VCCO_2 pins must be connected)."
      },
      {
        "number": "32",
        "name": "IO_L03P_2/D7/GCLK12",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration data D7 and global clock input GCLK12, then user I/O."
      },
      {
        "number": "33",
        "name": "IO_L03N_2/D6/GCLK13",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration data D6 and global clock input GCLK13, then user I/O."
      },
      {
        "number": "34",
        "name": "IO/D5",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration data D5, then user I/O."
      },
      {
        "number": "35",
        "name": "IO_L04P_2/D4/GCLK14",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration data D4 and global clock input GCLK14, then user I/O."
      },
      {
        "number": "36",
        "name": "IO_L04N_2/D3/GCLK15",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration data D3 and global clock input GCLK15, then user I/O."
      },
      {
        "number": "37",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "38",
        "name": "IP_L05P_2/RDWR_B/GCLK0",
        "type": "input",
        "description": "Bank 2 input-only dual-purpose pin; RDWR_B during configuration and global clock input GCLK0."
      },
      {
        "number": "39",
        "name": "IP_L05N_2/M2/GCLK1",
        "type": "input",
        "description": "Bank 2 input-only dual-purpose pin; configuration mode select M2 and global clock input GCLK1."
      },
      {
        "number": "40",
        "name": "IO_L06P_2/D2/GCLK2",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration data D2 and global clock input GCLK2, then user I/O."
      },
      {
        "number": "41",
        "name": "IO_L06N_2/D1/GCLK3",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration data D1 and global clock input GCLK3, then user I/O."
      },
      {
        "number": "42",
        "name": "IO/M1",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration mode select M1, then user I/O."
      },
      {
        "number": "43",
        "name": "IO_L07P_2/M0",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration mode select M0, then user I/O."
      },
      {
        "number": "44",
        "name": "IO_L07N_2/DIN/D0",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; serial data input DIN/D0 during configuration, then user I/O."
      },
      {
        "number": "45",
        "name": "VCCO_2",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 2 (all VCCO_2 pins must be connected)."
      },
      {
        "number": "46",
        "name": "VCCAUX",
        "type": "power_in",
        "description": "Auxiliary supply, +2.5V."
      },
      {
        "number": "47",
        "name": "IO_L08P_2/VS2",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; SPI variant select VS2 during configuration, then user I/O."
      },
      {
        "number": "48",
        "name": "IO_L08N_2/VS1",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; SPI variant select VS1 during configuration, then user I/O."
      },
      {
        "number": "49",
        "name": "IO_L09P_2/VS0",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; SPI variant select VS0 during configuration, then user I/O."
      },
      {
        "number": "50",
        "name": "IO_L09N_2/CCLK",
        "type": "bidirectional",
        "description": "Bank 2 dual-purpose pin; configuration clock CCLK, then user I/O."
      },
      {
        "number": "51",
        "name": "DONE",
        "type": "bidirectional",
        "description": "Dedicated open-drain configuration pin (powered by VCCAUX) that goes High when configuration completes; needs external 330 ohm pull-up to 2.5V."
      },
      {
        "number": "52",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "53",
        "name": "IO_L01P_1",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, true side of differential pair L01."
      },
      {
        "number": "54",
        "name": "IO_L01N_1",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, inverted side of differential pair L01."
      },
      {
        "number": "55",
        "name": "VCCO_1",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 1 (all VCCO_1 pins must be connected)."
      },
      {
        "number": "56",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply, +1.2V."
      },
      {
        "number": "57",
        "name": "IO_L02P_1",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, true side of differential pair L02."
      },
      {
        "number": "58",
        "name": "IO_L02N_1",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, inverted side of differential pair L02."
      },
      {
        "number": "59",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "60",
        "name": "IO_L03P_1/RHCLK0",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, true side of pair L03, or right-half clock input RHCLK0."
      },
      {
        "number": "61",
        "name": "IO_L03N_1/RHCLK1",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, inverted side of pair L03, or right-half clock input RHCLK1."
      },
      {
        "number": "62",
        "name": "IO_L04P_1/RHCLK2",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, true side of pair L04, or right-half clock input RHCLK2."
      },
      {
        "number": "63",
        "name": "IO_L04N_1/RHCLK3",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, inverted side of pair L04, or right-half clock input RHCLK3."
      },
      {
        "number": "64",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "65",
        "name": "IO_L05P_1/RHCLK4",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, true side of pair L05, or right-half clock input RHCLK4."
      },
      {
        "number": "66",
        "name": "IO_L05N_1/RHCLK5",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, inverted side of pair L05, or right-half clock input RHCLK5."
      },
      {
        "number": "67",
        "name": "IO_L06P_1/RHCLK6",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, true side of pair L06, or right-half clock input RHCLK6."
      },
      {
        "number": "68",
        "name": "IO_L06N_1/RHCLK7",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, inverted side of pair L06, or right-half clock input RHCLK7."
      },
      {
        "number": "69",
        "name": "IP/VREF_1",
        "type": "input",
        "description": "Bank 1 input-only pin that also serves as VREF input for bank 1 when HSTL/SSTL is used."
      },
      {
        "number": "70",
        "name": "IO_L07P_1",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, true side of differential pair L07."
      },
      {
        "number": "71",
        "name": "IO_L07N_1",
        "type": "bidirectional",
        "description": "Bank 1 user I/O, inverted side of differential pair L07."
      },
      {
        "number": "72",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "73",
        "name": "VCCO_1",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 1 (all VCCO_1 pins must be connected)."
      },
      {
        "number": "74",
        "name": "VCCAUX",
        "type": "power_in",
        "description": "Auxiliary supply, +2.5V."
      },
      {
        "number": "75",
        "name": "TMS",
        "type": "input",
        "description": "Dedicated JTAG test mode select pin, powered by VCCAUX."
      },
      {
        "number": "76",
        "name": "TDO",
        "type": "output",
        "description": "Dedicated JTAG test data output pin, powered by VCCAUX."
      },
      {
        "number": "77",
        "name": "TCK",
        "type": "input",
        "description": "Dedicated JTAG test clock input pin, powered by VCCAUX."
      },
      {
        "number": "78",
        "name": "IO_L01P_0",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, true side of differential pair L01."
      },
      {
        "number": "79",
        "name": "IO_L01N_0",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, inverted side of differential pair L01."
      },
      {
        "number": "80",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply, +1.2V."
      },
      {
        "number": "81",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "82",
        "name": "VCCO_0",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 0 (all VCCO_0 pins must be connected)."
      },
      {
        "number": "83",
        "name": "IO_L02P_0/GCLK4",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, true side of pair L02, or global clock input GCLK4."
      },
      {
        "number": "84",
        "name": "IO_L02N_0/GCLK5",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, inverted side of pair L02, or global clock input GCLK5."
      },
      {
        "number": "85",
        "name": "IO_L03P_0/GCLK6",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, true side of pair L03, or global clock input GCLK6."
      },
      {
        "number": "86",
        "name": "IO_L03N_0/GCLK7",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, inverted side of pair L03, or global clock input GCLK7."
      },
      {
        "number": "87",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "88",
        "name": "IP_L04P_0/GCLK8",
        "type": "input",
        "description": "Bank 0 input-only pin, true side of pair L04, or global clock input GCLK8."
      },
      {
        "number": "89",
        "name": "IP_L04N_0/GCLK9",
        "type": "input",
        "description": "Bank 0 input-only pin, inverted side of pair L04, or global clock input GCLK9."
      },
      {
        "number": "90",
        "name": "IO_L05P_0/GCLK10",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, true side of pair L05, or global clock input GCLK10."
      },
      {
        "number": "91",
        "name": "IO_L05N_0/GCLK11",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, inverted side of pair L05, or global clock input GCLK11."
      },
      {
        "number": "92",
        "name": "IO",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 0."
      },
      {
        "number": "93",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "94",
        "name": "IO_L06P_0",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, true side of differential pair L06."
      },
      {
        "number": "95",
        "name": "IO_L06N_0/VREF_0",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, inverted side of pair L06, or VREF input for bank 0 when HSTL/SSTL is used."
      },
      {
        "number": "96",
        "name": "VCCAUX",
        "type": "power_in",
        "description": "Auxiliary supply, +2.5V."
      },
      {
        "number": "97",
        "name": "VCCO_0",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 0 (all VCCO_0 pins must be connected)."
      },
      {
        "number": "98",
        "name": "IO_L07P_0",
        "type": "bidirectional",
        "description": "Bank 0 user I/O, true side of differential pair L07."
      },
      {
        "number": "99",
        "name": "IO_L07N_0/HSWAP",
        "type": "bidirectional",
        "description": "Bank 0 dual-purpose pin; HSWAP pull-up control during configuration (Low enables I/O pull-ups), then user I/O."
      },
      {
        "number": "100",
        "name": "TDI",
        "type": "input",
        "description": "Dedicated JTAG test data input pin, powered by VCCAUX."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: VQG100 pin numbers in Table 130 are printed with a 'P' prefix (e.g. P92); they are given here as pla",
          "27/100 pins cited to the wrong page (name found elsewhere): ['44:IO_L07N_2/DIN/D0@p163', '45:VCCO_2@p163', '46:VCCAUX@p164', '50:IO_L09N_2/CCLK@p163']"
        ],
        "pages_sent": 94,
        "cost_usd": 1.1571,
        "at": "2026-10-23T03:25:31"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/6dfdb8a51adc67c061be88553e165f26.pdf",
        "pages": 227,
        "sha256": "6c7c492700f5d306",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 100,
        "described": 100,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "xc3s250e-4vqg100i.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          16.0,
          16.0,
          1.5
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "51720097260ffba41c3062f85f67623721102fa535901c47cb555a1f444feeb3",
        "checked": "2026-10-23",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "xc3s250e-4vqg100i-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          16.0,
          16.0,
          1.5
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d3c401d9358d34c4a0b20c7af7faa816e8f3f789def0971972f0816fe96f68e6",
        "checked": "2026-10-23",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}