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XC3S250E-4VQG100I

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XILINX Programmable Logic Device (CPLDs/FPGAs), QFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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XC3S250E-4VQG100I

XILINX · Programmable Logic Device (CPLDs/FPGAs) · QFP-100(14x14)

XC3S250E-4VQG100I from XILINX, in a QFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PROG_B input Dedicated active-Low configuration pin (powered by VCCAUX) that restarts configuration when held Low for 500 ns or longer.
2 IO_L01P_3 bidirectional Bank 3 user I/O, true side of differential pair L01.
3 IO_L01N_3 bidirectional Bank 3 user I/O, inverted side of differential pair L01.
4 IO_L02P_3 bidirectional Bank 3 user I/O, true side of differential pair L02.
5 IO_L02N_3/VREF_3 bidirectional Bank 3 user I/O, inverted side of pair L02, or VREF input for bank 3 when an HSTL/SSTL standard is used.
6 VCCINT power_in Internal core logic supply, +1.2V.
7 GND power_in Ground.
8 VCCO_3 power_in Output voltage supply for I/O bank 3 (all VCCO_3 pins must be connected).
9 IO_L03P_3/LHCLK0 bidirectional Bank 3 user I/O, true side of pair L03, or left-half clock input LHCLK0.
10 IO_L03N_3/LHCLK1 bidirectional Bank 3 user I/O, inverted side of pair L03, or left-half clock input LHCLK1.
11 IO_L04P_3/LHCLK2 bidirectional Bank 3 user I/O, true side of pair L04, or left-half clock input LHCLK2.
12 IO_L04N_3/LHCLK3 bidirectional Bank 3 user I/O, inverted side of pair L04, or left-half clock input LHCLK3.
13 IP input Unrestricted general-purpose input-only pin in bank 3.
14 GND power_in Ground.
15 IO_L05P_3/LHCLK4 bidirectional Bank 3 user I/O, true side of pair L05, or left-half clock input LHCLK4.
16 IO_L05N_3/LHCLK5 bidirectional Bank 3 user I/O, inverted side of pair L05, or left-half clock input LHCLK5.
17 IO_L06P_3/LHCLK6 bidirectional Bank 3 user I/O, true side of pair L06, or left-half clock input LHCLK6.
18 IO_L06N_3/LHCLK7 bidirectional Bank 3 user I/O, inverted side of pair L06, or left-half clock input LHCLK7.
19 GND power_in Ground.
20 VCCO_3 power_in Output voltage supply for I/O bank 3 (all VCCO_3 pins must be connected).
21 VCCAUX power_in Auxiliary supply, +2.5V.
22 IO_L07P_3 bidirectional Bank 3 user I/O, true side of differential pair L07.
23 IO_L07N_3 bidirectional Bank 3 user I/O, inverted side of differential pair L07.
24 IO_L01P_2/CSO_B bidirectional Bank 2 dual-purpose pin, true side of pair L01; CSO_B chip-select output during configuration, then user I/O.
25 IO_L01N_2/INIT_B bidirectional Bank 2 dual-purpose pin; open-drain active-Low initialization indicator during configuration, then user I/O.
26 IO_L02P_2/DOUT/BUSY bidirectional Bank 2 dual-purpose pin; DOUT/BUSY output during configuration, then user I/O.
27 IO_L02N_2/MOSI/CSI_B bidirectional Bank 2 dual-purpose pin; MOSI or CSI_B during configuration, then user I/O.
28 VCCINT power_in Internal core logic supply, +1.2V.
29 GND power_in Ground.
30 IP/VREF_2 input Bank 2 input-only pin that also serves as VREF input for bank 2 when HSTL/SSTL is used.
31 VCCO_2 power_in Output voltage supply for I/O bank 2 (all VCCO_2 pins must be connected).
32 IO_L03P_2/D7/GCLK12 bidirectional Bank 2 dual-purpose pin; configuration data D7 and global clock input GCLK12, then user I/O.
33 IO_L03N_2/D6/GCLK13 bidirectional Bank 2 dual-purpose pin; configuration data D6 and global clock input GCLK13, then user I/O.
34 IO/D5 bidirectional Bank 2 dual-purpose pin; configuration data D5, then user I/O.
35 IO_L04P_2/D4/GCLK14 bidirectional Bank 2 dual-purpose pin; configuration data D4 and global clock input GCLK14, then user I/O.
36 IO_L04N_2/D3/GCLK15 bidirectional Bank 2 dual-purpose pin; configuration data D3 and global clock input GCLK15, then user I/O.
37 GND power_in Ground.
38 IP_L05P_2/RDWR_B/GCLK0 input Bank 2 input-only dual-purpose pin; RDWR_B during configuration and global clock input GCLK0.
39 IP_L05N_2/M2/GCLK1 input Bank 2 input-only dual-purpose pin; configuration mode select M2 and global clock input GCLK1.
40 IO_L06P_2/D2/GCLK2 bidirectional Bank 2 dual-purpose pin; configuration data D2 and global clock input GCLK2, then user I/O.
41 IO_L06N_2/D1/GCLK3 bidirectional Bank 2 dual-purpose pin; configuration data D1 and global clock input GCLK3, then user I/O.
42 IO/M1 bidirectional Bank 2 dual-purpose pin; configuration mode select M1, then user I/O.
43 IO_L07P_2/M0 bidirectional Bank 2 dual-purpose pin; configuration mode select M0, then user I/O.
44 IO_L07N_2/DIN/D0 bidirectional Bank 2 dual-purpose pin; serial data input DIN/D0 during configuration, then user I/O.
45 VCCO_2 power_in Output voltage supply for I/O bank 2 (all VCCO_2 pins must be connected).
46 VCCAUX power_in Auxiliary supply, +2.5V.
47 IO_L08P_2/VS2 bidirectional Bank 2 dual-purpose pin; SPI variant select VS2 during configuration, then user I/O.
48 IO_L08N_2/VS1 bidirectional Bank 2 dual-purpose pin; SPI variant select VS1 during configuration, then user I/O.
49 IO_L09P_2/VS0 bidirectional Bank 2 dual-purpose pin; SPI variant select VS0 during configuration, then user I/O.
50 IO_L09N_2/CCLK bidirectional Bank 2 dual-purpose pin; configuration clock CCLK, then user I/O.
51 DONE bidirectional Dedicated open-drain configuration pin (powered by VCCAUX) that goes High when configuration completes; needs external 330 ohm pull-up to 2.5V.
52 GND power_in Ground.
53 IO_L01P_1 bidirectional Bank 1 user I/O, true side of differential pair L01.
54 IO_L01N_1 bidirectional Bank 1 user I/O, inverted side of differential pair L01.
55 VCCO_1 power_in Output voltage supply for I/O bank 1 (all VCCO_1 pins must be connected).
56 VCCINT power_in Internal core logic supply, +1.2V.
57 IO_L02P_1 bidirectional Bank 1 user I/O, true side of differential pair L02.
58 IO_L02N_1 bidirectional Bank 1 user I/O, inverted side of differential pair L02.
59 GND power_in Ground.
60 IO_L03P_1/RHCLK0 bidirectional Bank 1 user I/O, true side of pair L03, or right-half clock input RHCLK0.
61 IO_L03N_1/RHCLK1 bidirectional Bank 1 user I/O, inverted side of pair L03, or right-half clock input RHCLK1.
62 IO_L04P_1/RHCLK2 bidirectional Bank 1 user I/O, true side of pair L04, or right-half clock input RHCLK2.
63 IO_L04N_1/RHCLK3 bidirectional Bank 1 user I/O, inverted side of pair L04, or right-half clock input RHCLK3.
64 GND power_in Ground.
65 IO_L05P_1/RHCLK4 bidirectional Bank 1 user I/O, true side of pair L05, or right-half clock input RHCLK4.
66 IO_L05N_1/RHCLK5 bidirectional Bank 1 user I/O, inverted side of pair L05, or right-half clock input RHCLK5.
67 IO_L06P_1/RHCLK6 bidirectional Bank 1 user I/O, true side of pair L06, or right-half clock input RHCLK6.
68 IO_L06N_1/RHCLK7 bidirectional Bank 1 user I/O, inverted side of pair L06, or right-half clock input RHCLK7.
69 IP/VREF_1 input Bank 1 input-only pin that also serves as VREF input for bank 1 when HSTL/SSTL is used.
70 IO_L07P_1 bidirectional Bank 1 user I/O, true side of differential pair L07.
71 IO_L07N_1 bidirectional Bank 1 user I/O, inverted side of differential pair L07.
72 GND power_in Ground.
73 VCCO_1 power_in Output voltage supply for I/O bank 1 (all VCCO_1 pins must be connected).
74 VCCAUX power_in Auxiliary supply, +2.5V.
75 TMS input Dedicated JTAG test mode select pin, powered by VCCAUX.
76 TDO output Dedicated JTAG test data output pin, powered by VCCAUX.
77 TCK input Dedicated JTAG test clock input pin, powered by VCCAUX.
78 IO_L01P_0 bidirectional Bank 0 user I/O, true side of differential pair L01.
79 IO_L01N_0 bidirectional Bank 0 user I/O, inverted side of differential pair L01.
80 VCCINT power_in Internal core logic supply, +1.2V.
81 GND power_in Ground.
82 VCCO_0 power_in Output voltage supply for I/O bank 0 (all VCCO_0 pins must be connected).
83 IO_L02P_0/GCLK4 bidirectional Bank 0 user I/O, true side of pair L02, or global clock input GCLK4.
84 IO_L02N_0/GCLK5 bidirectional Bank 0 user I/O, inverted side of pair L02, or global clock input GCLK5.
85 IO_L03P_0/GCLK6 bidirectional Bank 0 user I/O, true side of pair L03, or global clock input GCLK6.
86 IO_L03N_0/GCLK7 bidirectional Bank 0 user I/O, inverted side of pair L03, or global clock input GCLK7.
87 GND power_in Ground.
88 IP_L04P_0/GCLK8 input Bank 0 input-only pin, true side of pair L04, or global clock input GCLK8.
89 IP_L04N_0/GCLK9 input Bank 0 input-only pin, inverted side of pair L04, or global clock input GCLK9.
90 IO_L05P_0/GCLK10 bidirectional Bank 0 user I/O, true side of pair L05, or global clock input GCLK10.
91 IO_L05N_0/GCLK11 bidirectional Bank 0 user I/O, inverted side of pair L05, or global clock input GCLK11.
92 IO bidirectional Unrestricted general-purpose user I/O in bank 0.
93 GND power_in Ground.
94 IO_L06P_0 bidirectional Bank 0 user I/O, true side of differential pair L06.
95 IO_L06N_0/VREF_0 bidirectional Bank 0 user I/O, inverted side of pair L06, or VREF input for bank 0 when HSTL/SSTL is used.
96 VCCAUX power_in Auxiliary supply, +2.5V.
97 VCCO_0 power_in Output voltage supply for I/O bank 0 (all VCCO_0 pins must be connected).
98 IO_L07P_0 bidirectional Bank 0 user I/O, true side of differential pair L07.
99 IO_L07N_0/HSWAP bidirectional Bank 0 dual-purpose pin; HSWAP pull-up control during configuration (Low enables I/O pull-ups), then user I/O.
100 TDI input Dedicated JTAG test data input pin, powered by VCCAUX.

Key specifications

Parameter Value
Manufacturer XILINX
Package QFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Junction temperature range, Industrial (I grade) TJ -40 100 °C Industrial temperature range 6
Clock-to-output time, with DCM, -4 speed grade TICKOFDCM 3.45 ns LVCMOS25, 12 mA output drive, Fast slew rate, with DCM; XC3S250E 125
Clock-to-output time, without DCM, -4 speed grade TICKOF 5.43 ns LVCMOS25, 12 mA output drive, Fast slew rate, without DCM; XC3S250E 125
LVDS_25 VCCO for drivers VCCO 2.375 2.5 2.625 V LVDS_25 122
LVDS_25 differential input voltage VID 100 350 600 mV LVDS_25 122
LVDS_25 input common-mode voltage VICM 0.3 1.25 2.2 V LVDS_25 122

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Dedicated pins(6) -0.5, VCCAUX + 0.5 V TIN Input signal transition time(7), - 500 ns 117

CAD (KiCad official)

  • Symbol: XC3S250E-4VQG100I
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: QFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: xc3s250e-4vqg100i-etched.step / xc3s250e-4vqg100i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc3s250e-4vqg100i.step / xc3s250e-4vqg100i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XILINX datasheet (227 pp, sha256 6c7c492700f5d306, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF