XC3S200A-4VQG100C

{
  "slug": "xc3s200a-4vqg100c",
  "version": "0.1.0",
  "type": "component",
  "description": "XILINX Programmable Logic Device (CPLDs/FPGAs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "xc3s200a-4vqg100c",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
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  "files": [
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    "README.md",
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    "xc3s200a-4vqg100c.kicad_mod",
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    "docs/xc3s200a-4vqg100c-datasheet.pdf",
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    "xc3s200a-4vqg100c-hero.overlay.json",
    "xc3s200a-4vqg100c-etched.glb"
  ],
  "component": {
    "mpn": "XC3S200A-4VQG100C",
    "manufacturer": "XILINX",
    "package": "TQFP-100(14x14)",
    "pin_count": 100,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Programmable Logic Device (CPLDs/FPGAs)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589032409190289408",
    "parts": {
      "symbol": "xc3s200a-4vqg100c.kicad_sym",
      "footprint": "xc3s200a-4vqg100c.kicad_mod",
      "model_3d": "xc3s200a-4vqg100c-hero.glb",
      "model_3d_plain": "xc3s200a-4vqg100c-etched.glb",
      "model_3d_step": "xc3s200a-4vqg100c-etched.step",
      "model_3d_step_plain": "xc3s200a-4vqg100c.step",
      "lbr": "xc3s200a-4vqg100c.lbr"
    },
    "distributor_links": {
      "lcsc": "C1521645",
      "digikey": "122-1594-ND",
      "mouser": "217-C3S200A-4VQG100C"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T17:34:17Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "122-1594-ND",
        "status": "found",
        "lifecycle": "Obsolete"
      },
      "mouser": {
        "pn": "217-C3S200A-4VQG100C",
        "status": "found",
        "lifecycle": "End of Life"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "TMS",
        "type": "input",
        "description": "Dedicated JTAG test-mode-select pin, not a user I/O, powered by VCCAUX."
      },
      {
        "number": "2",
        "name": "TDI",
        "type": "input",
        "description": "Dedicated JTAG test-data-input pin, not a user I/O, powered by VCCAUX."
      },
      {
        "number": "3",
        "name": "IO_L01P_3",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 3, P side of differential pair 1."
      },
      {
        "number": "4",
        "name": "IO_L01N_3",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 3, N side of differential pair 1."
      },
      {
        "number": "5",
        "name": "IO_L02P_3",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 3, P side of differential pair 2."
      },
      {
        "number": "6",
        "name": "IO_L02N_3",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 3, N side of differential pair 2."
      },
      {
        "number": "7",
        "name": "IP_3/VREF_3",
        "type": "input",
        "description": "Input-only pin in bank 3 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "9",
        "name": "IO_L03P_3/LHCLK0",
        "type": "bidirectional",
        "description": "User I/O in bank 3 that can also act as a left-half global clock input (LHCLK0)."
      },
      {
        "number": "10",
        "name": "IO_L03N_3/LHCLK1",
        "type": "bidirectional",
        "description": "User I/O in bank 3 that can also act as a left-half global clock input (LHCLK1)."
      },
      {
        "number": "11",
        "name": "VCCO_3",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 3 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected."
      },
      {
        "number": "12",
        "name": "IO_L04P_3/LHCLK2",
        "type": "bidirectional",
        "description": "User I/O in bank 3 that can also act as a left-half clock input (LHCLK2)."
      },
      {
        "number": "13",
        "name": "IO_L04N_3/IRDY2/LHCLK3",
        "type": "bidirectional",
        "description": "User I/O in bank 3 that can also act as a left-half clock input (LHCLK3); IRDY2 is a PCI function pin."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "15",
        "name": "IO_L05P_3/TRDY2/LHCLK6",
        "type": "bidirectional",
        "description": "User I/O in bank 3 that can also act as a left-half clock input (LHCLK6); TRDY2 is a PCI function pin."
      },
      {
        "number": "16",
        "name": "IO_L05N_3/LHCLK7",
        "type": "bidirectional",
        "description": "User I/O in bank 3 that can also act as a left-half global clock input (LHCLK7)."
      },
      {
        "number": "17",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply; must be connected to +1.2V."
      },
      {
        "number": "18",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "19",
        "name": "IO_L06P_3",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 3, P side of differential pair 6."
      },
      {
        "number": "20",
        "name": "IO_L06N_3",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 3, N side of differential pair 6."
      },
      {
        "number": "21",
        "name": "IP_3",
        "type": "input",
        "description": "Unrestricted general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
      },
      {
        "number": "22",
        "name": "VCCAUX",
        "type": "power_in",
        "description": "Auxiliary supply, set on board to 2.5V or 3.3V; all VCCAUX pins must be connected."
      },
      {
        "number": "23",
        "name": "IO_L01P_2/M1",
        "type": "bidirectional",
        "description": "Dual-purpose pin used as configuration mode-select M1 during configuration, then usually a user I/O."
      },
      {
        "number": "24",
        "name": "IO_L02P_2/M2",
        "type": "bidirectional",
        "description": "Dual-purpose pin used as configuration mode-select M2 during configuration, then usually a user I/O."
      },
      {
        "number": "25",
        "name": "IO_L01N_2/M0",
        "type": "bidirectional",
        "description": "Dual-purpose pin used as configuration mode-select M0 during configuration, then usually a user I/O."
      },
      {
        "number": "26",
        "name": "VCCO_2",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 2 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected."
      },
      {
        "number": "27",
        "name": "IO_L02N_2/CSO_B",
        "type": "bidirectional",
        "description": "Dual-purpose configuration pin CSO_B, usable as a user I/O after configuration (see UG332)."
      },
      {
        "number": "28",
        "name": "IO_L03P_2/RDWR_B",
        "type": "bidirectional",
        "description": "Dual-purpose configuration pin RDWR_B, usable as a user I/O after configuration (see UG332)."
      },
      {
        "number": "29",
        "name": "IO_L03N_2/VS2",
        "type": "bidirectional",
        "description": "Dual-purpose variant-select pin VS2 on the XC3S200A, usable as a user I/O after configuration."
      },
      {
        "number": "30",
        "name": "IO_L04P_2/VS1",
        "type": "bidirectional",
        "description": "Dual-purpose variant-select pin VS1 on the XC3S200A, usable as a user I/O after configuration."
      },
      {
        "number": "31",
        "name": "IO_L04N_2/VS0",
        "type": "bidirectional",
        "description": "Dual-purpose variant-select pin VS0, usable as a user I/O after configuration."
      },
      {
        "number": "32",
        "name": "IO_L05P_2",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 2, P side of differential pair 5."
      },
      {
        "number": "33",
        "name": "IO_L05N_2",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 2, N side of differential pair 5 (XC3S200A alignment)."
      },
      {
        "number": "34",
        "name": "IO_L06P_2/D7",
        "type": "bidirectional",
        "description": "Dual-purpose data pin D7 on the XC3S200A during configuration, usable as a user I/O afterward."
      },
      {
        "number": "35",
        "name": "IO_L06N_2/D6",
        "type": "bidirectional",
        "description": "Dual-purpose configuration data pin D6, usable as a user I/O after configuration."
      },
      {
        "number": "36",
        "name": "IO_L07P_2/D5",
        "type": "bidirectional",
        "description": "Dual-purpose configuration data pin D5, usable as a user I/O after configuration."
      },
      {
        "number": "37",
        "name": "IO_L07N_2/D4",
        "type": "bidirectional",
        "description": "Dual-purpose configuration data pin D4, usable as a user I/O after configuration."
      },
      {
        "number": "38",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply; must be connected to +1.2V."
      },
      {
        "number": "39",
        "name": "IP_2/VREF_2",
        "type": "input",
        "description": "Input-only pin in bank 2 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference."
      },
      {
        "number": "40",
        "name": "IO_L08P_2/GCLK14",
        "type": "bidirectional",
        "description": "User I/O in bank 2 that can also drive a global clock buffer input (GCLK14)."
      },
      {
        "number": "41",
        "name": "IO_L08N_2/GCLK15",
        "type": "bidirectional",
        "description": "User I/O in bank 2 that can also drive a global clock buffer input (GCLK15)."
      },
      {
        "number": "42",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "43",
        "name": "IO_L09P_2/GCLK0",
        "type": "bidirectional",
        "description": "User I/O in bank 2 that can also drive a global clock buffer input (GCLK0)."
      },
      {
        "number": "44",
        "name": "IO_L09N_2/GCLK1",
        "type": "bidirectional",
        "description": "User I/O in bank 2 that can also drive a global clock buffer input (GCLK1)."
      },
      {
        "number": "45",
        "name": "VCCO_2",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 2 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected."
      },
      {
        "number": "46",
        "name": "IO_2/MOSI/CSI_B",
        "type": "bidirectional",
        "description": "Dual-purpose configuration pin MOSI/CSI_B, usable as a user I/O after configuration."
      },
      {
        "number": "47",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "48",
        "name": "IO_L10P_2/INIT_B",
        "type": "bidirectional",
        "description": "Dual-purpose configuration pin INIT_B, usable as a user I/O after configuration."
      },
      {
        "number": "49",
        "name": "IO_L10N_2/D3",
        "type": "bidirectional",
        "description": "Dual-purpose configuration data pin D3, usable as a user I/O after configuration."
      },
      {
        "number": "50",
        "name": "IO_L11P_2/D2",
        "type": "bidirectional",
        "description": "Dual-purpose configuration data pin D2, usable as a user I/O after configuration."
      },
      {
        "number": "51",
        "name": "IO_L12P_2/D0/DIN/MISO",
        "type": "bidirectional",
        "description": "Dual-purpose configuration data pin D0/DIN/MISO on the XC3S200A, usable as a user I/O after configuration."
      },
      {
        "number": "52",
        "name": "IO_L11N_2/D1",
        "type": "bidirectional",
        "description": "Dual-purpose configuration data pin D1 on the XC3S200A, usable as a user I/O after configuration."
      },
      {
        "number": "53",
        "name": "IO_L12N_2/CCLK",
        "type": "bidirectional",
        "description": "Dual-purpose configuration clock pin CCLK, usable as a user I/O after configuration."
      },
      {
        "number": "54",
        "name": "DONE",
        "type": "bidirectional",
        "description": "Dedicated configuration pin DONE, not a user I/O, powered by VCCAUX."
      },
      {
        "number": "55",
        "name": "VCCAUX",
        "type": "power_in",
        "description": "Auxiliary supply, set on board to 2.5V or 3.3V; all VCCAUX pins must be connected."
      },
      {
        "number": "56",
        "name": "IO_L01P_1",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 1, P side of differential pair 1."
      },
      {
        "number": "57",
        "name": "IO_L01N_1",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 1, N side of differential pair 1."
      },
      {
        "number": "58",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "59",
        "name": "IO_L02P_1/RHCLK0",
        "type": "bidirectional",
        "description": "User I/O in bank 1 that can also act as a right-half clock input (RHCLK0)."
      },
      {
        "number": "60",
        "name": "IO_L02N_1/RHCLK1",
        "type": "bidirectional",
        "description": "User I/O in bank 1 that can also act as a right-half clock input (RHCLK1)."
      },
      {
        "number": "61",
        "name": "IO_L03P_1/RHCLK2",
        "type": "bidirectional",
        "description": "User I/O in bank 1 that can also act as a right-half clock input (RHCLK2)."
      },
      {
        "number": "62",
        "name": "IO_L03N_1/TRDY1/RHCLK3",
        "type": "bidirectional",
        "description": "User I/O in bank 1 that can also act as a right-half clock input (RHCLK3); TRDY1 is a PCI function pin."
      },
      {
        "number": "63",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "64",
        "name": "IO_L04P_1/IRDY1/RHCLK6",
        "type": "bidirectional",
        "description": "User I/O in bank 1 that can also act as a right-half clock input (RHCLK6); IRDY1 is a PCI function pin."
      },
      {
        "number": "65",
        "name": "IO_L04N_1/RHCLK7",
        "type": "bidirectional",
        "description": "User I/O in bank 1 that can also act as a right-half clock input (RHCLK7)."
      },
      {
        "number": "66",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply; must be connected to +1.2V."
      },
      {
        "number": "67",
        "name": "VCCO_1",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 1 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected."
      },
      {
        "number": "68",
        "name": "IP_1/VREF_1",
        "type": "input",
        "description": "Input-only pin in bank 1 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference."
      },
      {
        "number": "69",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "70",
        "name": "IO_L05P_1",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 1, P side of differential pair 5."
      },
      {
        "number": "71",
        "name": "IO_L05N_1",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 1, N side of differential pair 5."
      },
      {
        "number": "72",
        "name": "IO_L06P_1",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 1, P side of differential pair 6."
      },
      {
        "number": "73",
        "name": "IO_L06N_1",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 1, N side of differential pair 6."
      },
      {
        "number": "74",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "75",
        "name": "TDO",
        "type": "output",
        "description": "Dedicated JTAG test-data-output pin, not a user I/O, powered by VCCAUX."
      },
      {
        "number": "76",
        "name": "TCK",
        "type": "input",
        "description": "Dedicated JTAG test-clock pin, not a user I/O, powered by VCCAUX."
      },
      {
        "number": "77",
        "name": "IO_L01P_0/VREF_0",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also supply a voltage reference; all VREF pins in the bank must be connected if used."
      },
      {
        "number": "78",
        "name": "IO_L01N_0",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 0, N side of differential pair 1."
      },
      {
        "number": "79",
        "name": "VCCO_0",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 0 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected."
      },
      {
        "number": "80",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "81",
        "name": "VCCINT",
        "type": "power_in",
        "description": "Internal core logic supply; must be connected to +1.2V."
      },
      {
        "number": "82",
        "name": "IP_0/VREF_0",
        "type": "input",
        "description": "Input-only pin in bank 0 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference."
      },
      {
        "number": "83",
        "name": "IO_L02P_0/GCLK4",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also drive a global clock buffer input (GCLK4)."
      },
      {
        "number": "84",
        "name": "IO_L02N_0/GCLK5",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also drive a global clock buffer input (GCLK5)."
      },
      {
        "number": "85",
        "name": "IO_L03P_0/GCLK6",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also drive a global clock buffer input (GCLK6)."
      },
      {
        "number": "86",
        "name": "IO_L03N_0/GCLK7",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also drive a global clock buffer input (GCLK7)."
      },
      {
        "number": "87",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "88",
        "name": "IO_L04P_0/GCLK8",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also drive a global clock buffer input (GCLK8)."
      },
      {
        "number": "89",
        "name": "IO_L04N_0/GCLK9",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also drive a global clock buffer input (GCLK9)."
      },
      {
        "number": "90",
        "name": "IO_0/GCLK11",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also drive a global clock buffer input (GCLK11)."
      },
      {
        "number": "91",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "92",
        "name": "VCCAUX",
        "type": "power_in",
        "description": "Auxiliary supply, set on board to 2.5V or 3.3V; all VCCAUX pins must be connected."
      },
      {
        "number": "93",
        "name": "IO_L05P_0",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 0, P side of differential pair 5."
      },
      {
        "number": "94",
        "name": "IO_L05N_0",
        "type": "bidirectional",
        "description": "Unrestricted general-purpose user I/O in bank 0, N side of differential pair 5."
      },
      {
        "number": "95",
        "name": "GND",
        "type": "power_in",
        "description": "Ground return pin; all GND pins must be connected."
      },
      {
        "number": "96",
        "name": "VCCO_0",
        "type": "power_in",
        "description": "Output voltage supply for I/O bank 0 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected."
      },
      {
        "number": "97",
        "name": "IP_0",
        "type": "input",
        "description": "Unrestricted general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode."
      },
      {
        "number": "98",
        "name": "IO_L06P_0/VREF_0",
        "type": "bidirectional",
        "description": "User I/O in bank 0 that can also supply a voltage reference; all VREF pins in the bank must be connected if used."
      },
      {
        "number": "99",
        "name": "IO_L06N_0/PUDC_B",
        "type": "bidirectional",
        "description": "Dual-purpose PUDC_B pin, usable as a user I/O after configuration (see UG332)."
      },
      {
        "number": "100",
        "name": "PROG_B",
        "type": "input",
        "description": "Dedicated configuration pin PROG_B, not a user I/O, powered by VCCAUX (see UG332)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package choice: the MPN suffix VQG100 is the Pb-free version of the VQ100 package. Table 62 (VQ100 p; Table 62 lists both XC3S50A and XC3S200A names for six differential pins that differ between the two; The datasheet says the VQ100 does not support Suspend mode (SUSPEND and AWAKE are not connected) and",
          "31/100 pins cited to the wrong page (name found elsewhere): ['31:IO_L04N_2/VS0@p70', '41:IO_L08N_2/GCLK15@p70', '44:IO_L09N_2/GCLK1@p70', '46:IO_2/MOSI/CSI_B@p70']"
        ],
        "pages_sent": 82,
        "cost_usd": 0.7717,
        "at": "2026-10-20T17:32:05"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589032409190289408",
        "pages": 132,
        "sha256": "f8f45f8464f50e74",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 100,
        "described": 100,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "xc3s200a-4vqg100c.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          16.0,
          16.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "99d530be126138ea024746562f1110203db0273456e99932e7e1930dc9f5fba5",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "xc3s200a-4vqg100c-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          16.0,
          16.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3f86608aa3cac2419df5c2a476093590543c694efd5accabe12aa77d22857a78",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}