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XC3S200A-4VQG100C

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XILINX Programmable Logic Device (CPLDs/FPGAs), TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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XC3S200A-4VQG100C

XILINX · Programmable Logic Device (CPLDs/FPGAs) · TQFP-100(14x14)

XC3S200A-4VQG100C from XILINX, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TMS input Dedicated JTAG test-mode-select pin, not a user I/O, powered by VCCAUX.
2 TDI input Dedicated JTAG test-data-input pin, not a user I/O, powered by VCCAUX.
3 IO_L01P_3 bidirectional Unrestricted general-purpose user I/O in bank 3, P side of differential pair 1.
4 IO_L01N_3 bidirectional Unrestricted general-purpose user I/O in bank 3, N side of differential pair 1.
5 IO_L02P_3 bidirectional Unrestricted general-purpose user I/O in bank 3, P side of differential pair 2.
6 IO_L02N_3 bidirectional Unrestricted general-purpose user I/O in bank 3, N side of differential pair 2.
7 IP_3/VREF_3 input Input-only pin in bank 3 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference.
8 GND power_in Ground return pin; all GND pins must be connected.
9 IO_L03P_3/LHCLK0 bidirectional User I/O in bank 3 that can also act as a left-half global clock input (LHCLK0).
10 IO_L03N_3/LHCLK1 bidirectional User I/O in bank 3 that can also act as a left-half global clock input (LHCLK1).
11 VCCO_3 power_in Output voltage supply for I/O bank 3 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected.
12 IO_L04P_3/LHCLK2 bidirectional User I/O in bank 3 that can also act as a left-half clock input (LHCLK2).
13 IO_L04N_3/IRDY2/LHCLK3 bidirectional User I/O in bank 3 that can also act as a left-half clock input (LHCLK3); IRDY2 is a PCI function pin.
14 GND power_in Ground return pin; all GND pins must be connected.
15 IO_L05P_3/TRDY2/LHCLK6 bidirectional User I/O in bank 3 that can also act as a left-half clock input (LHCLK6); TRDY2 is a PCI function pin.
16 IO_L05N_3/LHCLK7 bidirectional User I/O in bank 3 that can also act as a left-half global clock input (LHCLK7).
17 VCCINT power_in Internal core logic supply; must be connected to +1.2V.
18 GND power_in Ground return pin; all GND pins must be connected.
19 IO_L06P_3 bidirectional Unrestricted general-purpose user I/O in bank 3, P side of differential pair 6.
20 IO_L06N_3 bidirectional Unrestricted general-purpose user I/O in bank 3, N side of differential pair 6.
21 IP_3 input Unrestricted general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
22 VCCAUX power_in Auxiliary supply, set on board to 2.5V or 3.3V; all VCCAUX pins must be connected.
23 IO_L01P_2/M1 bidirectional Dual-purpose pin used as configuration mode-select M1 during configuration, then usually a user I/O.
24 IO_L02P_2/M2 bidirectional Dual-purpose pin used as configuration mode-select M2 during configuration, then usually a user I/O.
25 IO_L01N_2/M0 bidirectional Dual-purpose pin used as configuration mode-select M0 during configuration, then usually a user I/O.
26 VCCO_2 power_in Output voltage supply for I/O bank 2 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected.
27 IO_L02N_2/CSO_B bidirectional Dual-purpose configuration pin CSO_B, usable as a user I/O after configuration (see UG332).
28 IO_L03P_2/RDWR_B bidirectional Dual-purpose configuration pin RDWR_B, usable as a user I/O after configuration (see UG332).
29 IO_L03N_2/VS2 bidirectional Dual-purpose variant-select pin VS2 on the XC3S200A, usable as a user I/O after configuration.
30 IO_L04P_2/VS1 bidirectional Dual-purpose variant-select pin VS1 on the XC3S200A, usable as a user I/O after configuration.
31 IO_L04N_2/VS0 bidirectional Dual-purpose variant-select pin VS0, usable as a user I/O after configuration.
32 IO_L05P_2 bidirectional Unrestricted general-purpose user I/O in bank 2, P side of differential pair 5.
33 IO_L05N_2 bidirectional Unrestricted general-purpose user I/O in bank 2, N side of differential pair 5 (XC3S200A alignment).
34 IO_L06P_2/D7 bidirectional Dual-purpose data pin D7 on the XC3S200A during configuration, usable as a user I/O afterward.
35 IO_L06N_2/D6 bidirectional Dual-purpose configuration data pin D6, usable as a user I/O after configuration.
36 IO_L07P_2/D5 bidirectional Dual-purpose configuration data pin D5, usable as a user I/O after configuration.
37 IO_L07N_2/D4 bidirectional Dual-purpose configuration data pin D4, usable as a user I/O after configuration.
38 VCCINT power_in Internal core logic supply; must be connected to +1.2V.
39 IP_2/VREF_2 input Input-only pin in bank 2 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference.
40 IO_L08P_2/GCLK14 bidirectional User I/O in bank 2 that can also drive a global clock buffer input (GCLK14).
41 IO_L08N_2/GCLK15 bidirectional User I/O in bank 2 that can also drive a global clock buffer input (GCLK15).
42 GND power_in Ground return pin; all GND pins must be connected.
43 IO_L09P_2/GCLK0 bidirectional User I/O in bank 2 that can also drive a global clock buffer input (GCLK0).
44 IO_L09N_2/GCLK1 bidirectional User I/O in bank 2 that can also drive a global clock buffer input (GCLK1).
45 VCCO_2 power_in Output voltage supply for I/O bank 2 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected.
46 IO_2/MOSI/CSI_B bidirectional Dual-purpose configuration pin MOSI/CSI_B, usable as a user I/O after configuration.
47 GND power_in Ground return pin; all GND pins must be connected.
48 IO_L10P_2/INIT_B bidirectional Dual-purpose configuration pin INIT_B, usable as a user I/O after configuration.
49 IO_L10N_2/D3 bidirectional Dual-purpose configuration data pin D3, usable as a user I/O after configuration.
50 IO_L11P_2/D2 bidirectional Dual-purpose configuration data pin D2, usable as a user I/O after configuration.
51 IO_L12P_2/D0/DIN/MISO bidirectional Dual-purpose configuration data pin D0/DIN/MISO on the XC3S200A, usable as a user I/O after configuration.
52 IO_L11N_2/D1 bidirectional Dual-purpose configuration data pin D1 on the XC3S200A, usable as a user I/O after configuration.
53 IO_L12N_2/CCLK bidirectional Dual-purpose configuration clock pin CCLK, usable as a user I/O after configuration.
54 DONE bidirectional Dedicated configuration pin DONE, not a user I/O, powered by VCCAUX.
55 VCCAUX power_in Auxiliary supply, set on board to 2.5V or 3.3V; all VCCAUX pins must be connected.
56 IO_L01P_1 bidirectional Unrestricted general-purpose user I/O in bank 1, P side of differential pair 1.
57 IO_L01N_1 bidirectional Unrestricted general-purpose user I/O in bank 1, N side of differential pair 1.
58 GND power_in Ground return pin; all GND pins must be connected.
59 IO_L02P_1/RHCLK0 bidirectional User I/O in bank 1 that can also act as a right-half clock input (RHCLK0).
60 IO_L02N_1/RHCLK1 bidirectional User I/O in bank 1 that can also act as a right-half clock input (RHCLK1).
61 IO_L03P_1/RHCLK2 bidirectional User I/O in bank 1 that can also act as a right-half clock input (RHCLK2).
62 IO_L03N_1/TRDY1/RHCLK3 bidirectional User I/O in bank 1 that can also act as a right-half clock input (RHCLK3); TRDY1 is a PCI function pin.
63 GND power_in Ground return pin; all GND pins must be connected.
64 IO_L04P_1/IRDY1/RHCLK6 bidirectional User I/O in bank 1 that can also act as a right-half clock input (RHCLK6); IRDY1 is a PCI function pin.
65 IO_L04N_1/RHCLK7 bidirectional User I/O in bank 1 that can also act as a right-half clock input (RHCLK7).
66 VCCINT power_in Internal core logic supply; must be connected to +1.2V.
67 VCCO_1 power_in Output voltage supply for I/O bank 1 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected.
68 IP_1/VREF_1 input Input-only pin in bank 1 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference.
69 GND power_in Ground return pin; all GND pins must be connected.
70 IO_L05P_1 bidirectional Unrestricted general-purpose user I/O in bank 1, P side of differential pair 5.
71 IO_L05N_1 bidirectional Unrestricted general-purpose user I/O in bank 1, N side of differential pair 5.
72 IO_L06P_1 bidirectional Unrestricted general-purpose user I/O in bank 1, P side of differential pair 6.
73 IO_L06N_1 bidirectional Unrestricted general-purpose user I/O in bank 1, N side of differential pair 6.
74 GND power_in Ground return pin; all GND pins must be connected.
75 TDO output Dedicated JTAG test-data-output pin, not a user I/O, powered by VCCAUX.
76 TCK input Dedicated JTAG test-clock pin, not a user I/O, powered by VCCAUX.
77 IO_L01P_0/VREF_0 bidirectional User I/O in bank 0 that can also supply a voltage reference; all VREF pins in the bank must be connected if used.
78 IO_L01N_0 bidirectional Unrestricted general-purpose user I/O in bank 0, N side of differential pair 1.
79 VCCO_0 power_in Output voltage supply for I/O bank 0 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected.
80 GND power_in Ground return pin; all GND pins must be connected.
81 VCCINT power_in Internal core logic supply; must be connected to +1.2V.
82 IP_0/VREF_0 input Input-only pin in bank 0 that also serves as a voltage reference input; all VREF pins in the bank must be connected if used for a reference.
83 IO_L02P_0/GCLK4 bidirectional User I/O in bank 0 that can also drive a global clock buffer input (GCLK4).
84 IO_L02N_0/GCLK5 bidirectional User I/O in bank 0 that can also drive a global clock buffer input (GCLK5).
85 IO_L03P_0/GCLK6 bidirectional User I/O in bank 0 that can also drive a global clock buffer input (GCLK6).
86 IO_L03N_0/GCLK7 bidirectional User I/O in bank 0 that can also drive a global clock buffer input (GCLK7).
87 GND power_in Ground return pin; all GND pins must be connected.
88 IO_L04P_0/GCLK8 bidirectional User I/O in bank 0 that can also drive a global clock buffer input (GCLK8).
89 IO_L04N_0/GCLK9 bidirectional User I/O in bank 0 that can also drive a global clock buffer input (GCLK9).
90 IO_0/GCLK11 bidirectional User I/O in bank 0 that can also drive a global clock buffer input (GCLK11).
91 GND power_in Ground return pin; all GND pins must be connected.
92 VCCAUX power_in Auxiliary supply, set on board to 2.5V or 3.3V; all VCCAUX pins must be connected.
93 IO_L05P_0 bidirectional Unrestricted general-purpose user I/O in bank 0, P side of differential pair 5.
94 IO_L05N_0 bidirectional Unrestricted general-purpose user I/O in bank 0, N side of differential pair 5.
95 GND power_in Ground return pin; all GND pins must be connected.
96 VCCO_0 power_in Output voltage supply for I/O bank 0 that also sets input thresholds for some standards; all VCCO pins in the bank must be connected.
97 IP_0 input Unrestricted general-purpose input-only pin with no output structure, differential termination resistor, or PCI clamp diode.
98 IO_L06P_0/VREF_0 bidirectional User I/O in bank 0 that can also supply a voltage reference; all VREF pins in the bank must be connected if used.
99 IO_L06N_0/PUDC_B bidirectional Dual-purpose PUDC_B pin, usable as a user I/O after configuration (see UG332).
100 PROG_B input Dedicated configuration pin PROG_B, not a user I/O, powered by VCCAUX (see UG332).

Key specifications

Parameter Value
Manufacturer XILINX
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal supply voltage VCCINT -0.5 1.32 V 11
Auxiliary supply voltage VCCAUX -0.5 3.75 V 11
Output driver supply voltage VCCO -0.5 3.75 V 11
Input reference voltage VREF -0.5 V Printed max is VCCO + 0.5 V (expression) 11
Voltage applied to all User I/O and dual-purpose pins VIN -0.95 4.6 V Driver in a high-impedance state 11
Voltage applied to all Dedicated pins VIN -0.5 4.6 V Dedicated pins 11
Input clamp current per I/O pin IIK -100 100 mA -0.5V < VIN < (VCCO + 0.5V); upper clamp only for PCI IOSTANDARDs 11
Electrostatic discharge voltage, human body model VESD -2000 2000 V Human body model 11
Electrostatic discharge voltage, charged device model VESD -500 500 V Charged device model 11
Electrostatic discharge voltage, machine model VESD -200 200 V Machine model 11
Junction temperature TJ 125 °C 11
Storage temperature TSTG -65 150 °C 11
Threshold for the VCCINT supply VCCINTT 0.4 1 V Power-on reset threshold 12
Threshold for the VCCAUX supply VCCAUXT 1 2 V Power-on reset threshold 12
Threshold for the VCCO Bank 2 supply VCCO2T 1 2 V Power-on reset threshold 12
Ramp rate from GND to valid VCCINT supply level VCCINTR 0.2 100 ms 12
Ramp rate from GND to valid VCCAUX supply level VCCAUXR 0.2 100 ms 12
Ramp rate from GND to valid VCCO Bank 2 supply level VCCO2R 0.2 100 ms 12
VCCINT level required to retain CCL and RAM data VDRINT 1 V 12
VCCAUX level required to retain CCL and RAM data VDRAUX 2 V 12
Junction temperature, commercial TJ 0 85 °C Commercial 13
Internal supply voltage VCCINT 1.14 1.2 1.26 V 13
Output driver supply voltage VCCO 1.1 3.6 V Spans all supported I/O standards 13
Auxiliary supply voltage VCCAUX 2.25 2.5 2.75 V VCCAUX = 2.5 setting 13
Auxiliary supply voltage VCCAUX 3 3.3 3.6 V VCCAUX = 3.3 setting 13
Input voltage, PCI IOSTANDARD VIN -0.5 V Printed max is -VCCO+0.5 V (expression) 13
Input voltage, IP or IO_#, all other IOSTANDARDs VIN -0.5 4.1 V All other IOSTANDARDs 13
Input voltage, IO_Lxxy_#, all other IOSTANDARDs VIN -0.5 4.1 V All other IOSTANDARDs 13
Input signal transition time TIN 500 ns Measured between 10% and 90% VCCO 13
Leakage current at User I/O, input-only, dual-purpose, and dedicated pins IL -10 10 µA Driver high-impedance, VIN = 0V or VCCO max, sample-tested 14
Leakage current on pins during hot socketing IHS -10 10 µA FPGA unpowered; all pins except INIT_B, PROG_B, DONE and JTAG when PUDC_B = 1 14
VREF current per pin IREF -10 10 µA All VCCO levels 14
Input capacitance CIN 10 pF 14
Current through pull-up resistor at User I/O, dual-purpose, input-only, and dedicated pins IRPU -151 -315 -710 µA VIN = GND; VCCO or VCCAUX = 3.0 V to 3.6 V 14
Current through pull-up resistor at User I/O, dual-purpose, input-only, and dedicated pins IRPU -82 -182 -437 µA VIN = GND; VCCO or VCCAUX = 2.3 V to 2.7 V 14
Current through pull-up resistor at User I/O, dual-purpose, input-only, and dedicated pins IRPU -36 -88 -226 µA VIN = GND; VCCO = 1.7 V to 1.9 V 14
Current through pull-up resistor at User I/O, dual-purpose, input-only, and dedicated pins IRPU -22 -56 -148 µA VIN = GND; VCCO = 1.4 V to 1.6 V 14
Current through pull-up resistor at User I/O, dual-purpose, input-only, and dedicated pins IRPU -11 -31 -83 µA VIN = GND; VCCO = 1.14 V to 1.26 V 14
Equivalent pull-up resistor value at User I/O, dual-purpose, input-only, and dedicated pins RPU 5.1 11.4 23.9 kΩ VIN = GND; VCCO = 3.0 V to 3.6 V 14
Equivalent pull-up resistor value at User I/O, dual-purpose, input-only, and dedicated pins RPU 6.2 14.8 33.1 kΩ VIN = GND; VCCO = 2.3 V to 2.7 V 14
Equivalent pull-up resistor value at User I/O, dual-purpose, input-only, and dedicated pins RPU 8.4 21.6 52.6 kΩ VIN = GND; VCCO = 1.7 V to 1.9 V 14
Equivalent pull-up resistor value at User I/O, dual-purpose, input-only, and dedicated pins RPU 10.8 28.4 74 kΩ VIN = GND; VCCO = 1.4 V to 1.6 V 14
Equivalent pull-up resistor value at User I/O, dual-purpose, input-only, and dedicated pins RPU 15.3 41.1 119.4 kΩ VIN = GND; VCCO = 1.14 V to 1.26 V 14
Current through pull-down resistor at User I/O, dual-purpose, input-only, and dedicated pins IRPD 167 346 659 µA VIN = VCCO; VCCAUX = 3.0 V to 3.6 V 14
Current through pull-down resistor at User I/O, dual-purpose, input-only, and dedicated pins IRPD 100 225 457 µA VIN = VCCO; VCCAUX = 2.25 V to 2.75 V 14
Resistance of optional differential termination circuit RDT 90 100 115 Ω VCCO = 3.3V ± 10%, LVDS_33, MINI_LVDS_33, RSDS_33 14
Resistance of optional differential termination circuit RDT 90 110 Ω VCCO = 2.5V ± 10%, LVDS_25, MINI_LVDS_25, RSDS_25 14
Quiescent VCCINT supply current, XC3S200A commercial ICCINTQ 7 50 mA Commercial maximum; blank configuration; I/Os high-impedance, pull-ups disabled 15
Quiescent VCCO supply current, XC3S200A commercial ICCOQ 0.2 2 mA Commercial maximum; blank configuration; I/Os high-impedance, pull-ups disabled 15
Quiescent VCCAUX supply current, XC3S200A commercial ICCAUXQ 5 12 mA Commercial maximum; blank configuration; I/Os high-impedance, pull-ups disabled 15
Input voltage low, LVTTL/LVCMOS33 (VIL max) VIL 0.8 V LVCMOS33, VCCO = 3.0 V to 3.6 V 16
Input voltage high, LVCMOS33 (VIH min) VIH 2 V LVCMOS33, VCCO = 3.0 V to 3.6 V 16
Input voltage low, LVCMOS25 (VIL max) VIL 0.7 V LVCMOS25, VCCO = 2.3 V to 2.7 V 16
Input voltage high, LVCMOS25 (VIH min) VIH 1.7 V LVCMOS25, VCCO = 2.3 V to 2.7 V 16
Input voltage low, LVCMOS18 (VIL max) VIL 0.4 V LVCMOS18, VCCO = 1.65 V to 1.95 V 16
Input voltage high, LVCMOS18 (VIH min) VIH 0.8 V LVCMOS18, VCCO = 1.65 V to 1.95 V 16
Low-level output voltage, LVTTL (VOL max) VOL 0.4 V LVTTL, all drive strengths 2 mA to 24 mA 17
High-level output voltage, LVTTL (VOH min) VOH 2.4 V LVTTL, all drive strengths 2 mA to 24 mA 17

CAD (KiCad official)

  • Symbol: XC3S200A-4VQG100C
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: xc3s200a-4vqg100c-etched.step / xc3s200a-4vqg100c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); xc3s200a-4vqg100c.step / xc3s200a-4vqg100c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XILINX datasheet (132 pp, sha256 f8f45f8464f50e74, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF