main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers wsp14n10: viewers · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago
wsp14n10-etched.glb Publish 0.1.0 · Ray 17d ago
wsp14n10-etched.step wsp14n10: factory component page (tier=lcsc) · Ray 17d ago
wsp14n10-hero.glb wsp14n10: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
wsp14n10-hero.overlay.json Publish 0.1.0 · Ray 17d ago
wsp14n10.glb Publish 0.1.0 · Ray 17d ago
wsp14n10.kicad_mod Publish 0.1.0 · Ray 17d ago
wsp14n10.kicad_sym Publish 0.1.0 · Ray 17d ago
wsp14n10.lbr Publish 0.1.0 · Ray 17d ago
wsp14n10.step Publish 0.1.0 · Ray 17d ago

WSP14N10

Winsok Semicon · MOSFETs · SOP-8

WSP14N10 from Winsok Semicon, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the N-channel MOSFET, tied with pins 2 and 3; continuous drain current is rated 14 A at TC=25°C.
2 S passive Source of the N-channel MOSFET, tied with pins 1 and 3.
3 S passive Source of the N-channel MOSFET, tied with pins 1 and 2.
4 G input Gate of the N-channel MOSFET, with a gate-source voltage rating of ±20 V and a threshold of 1.0 to 2.5 V.
5 D passive Drain of the N-channel MOSFET, tied with pins 6 to 8; drain-source voltage rating is 100 V.
6 D passive Drain of the N-channel MOSFET, tied with pins 5, 7 and 8.
7 D passive Drain of the N-channel MOSFET, tied with pins 5, 6 and 8.
8 D passive Drain of the N-channel MOSFET, tied with pins 5 to 7.

Key specifications

Parameter Value
Manufacturer Winsok Semicon
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 100 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID 14 A ID@TC=25℃, VGS @ 10V 1
Pulsed Drain Current IDM 42 A 1
Single Pulse Avalanche Energy EAS 30 mJ L=0.1mH 1
Total Power Dissipation PD 72 W TA=25℃ 1
Storage Temperature Range TSTG -55 150 ℃ 1
Operating Junction Temperature Range TJ -55 150 ℃ 1
Thermal Resistance Junction-ambient RθJA 40 ℃/W 1
Thermal Resistance Junction-Case RθJC 24 ℃/W 1
Drain-Source Breakdown Voltage BVDSS 100 V VGS=0V, ID=250uA 2
Static Drain-Source On-Resistance RDS(ON) 16 20 mΩ VGS=10V, ID=8A 2
Static Drain-Source On-Resistance RDS(ON) 25 28 mΩ VGS=4.5V, ID=6A 2
Gate Threshold Voltage VGS(th) 1 1.5 2.5 V VGS=VDS, ID=250uA 2
Drain-Source Leakage Current IDSS 1 uA VDS=100V, VGS=0V, TJ=25℃ 2
Drain-Source Leakage Current IDSS 5 uA VDS=100V, VGS=0V, TJ=55℃ 2
Gate-Source Leakage Current IGSS -100 100 nA VGS=±20V, VDS=0V 2
Gate Resistance Rg 0.55 1 Ω VDS=0V, VGS=0V, f=1MHz 2
Continuous Source Current IS 40 A VG=VD=0V, Force Current 2
Diode Forward Voltage VSD 1.3 V VGS=0V, IS=8A, TJ=25℃ 2
BVDSS Temperature Coefficient ΔBVDSS/ΔTJ 0.098 V/℃ Reference to 25℃, ID=1mA 2
VGS(th) Temperature Coefficient ΔVGS(th) -5.52 mV/℃ 2
Total Gate Charge (10V) Qg 19.8 nC VDS=50V, VGS=10V, ID=8A 2
Gate-Source Charge Qgs 2.4 nC VDS=50V, VGS=10V, ID=8A 2
Gate-Drain Charge Qgd 5.3 nC VDS=50V, VGS=10V, ID=8A 2
Turn-On Delay Time Td(on) 17.8 ns VDD=50V, VGS=10V, RG=2.2Ω, ID=10A 2
Rise Time Tr 3.9 ns VDD=50V, VGS=10V, RG=2.2Ω, ID=10A 2
Turn-Off Delay Time Td(off) 33.5 ns VDD=50V, VGS=10V, RG=2.2Ω, ID=10A 2
Fall Time Tf 3.2 ns VDD=50V, VGS=10V, RG=2.2Ω, ID=10A 2
Input Capacitance Ciss 1191 pF VDS=50V, VGS=0V, f=1MHz 2
Output Capacitance Coss 195 pF VDS=50V, VGS=0V, f=1MHz 2
Reverse Transfer Capacitance Crss 41 pF VDS=50V, VGS=0V, f=1MHz 2
Reverse Recovery Time trr 50 nS IF=8A, dI/dt=100A/µs, TJ=25℃ 2
Reverse Recovery Charge Qrr 95 nC IF=8A, dI/dt=100A/µs, TJ=25℃ 2

CAD (KiCad official)

  • Symbol: WSP14N10
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: wsp14n10-etched.step / wsp14n10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); wsp14n10.step / wsp14n10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Winsok Semicon datasheet (6 pp, sha256 22603661cc29c575, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF