WM8761CBGED

{
  "slug": "wm8761cbged",
  "version": "0.1.0",
  "type": "component",
  "description": "Cirrus Logic Digital To Analog Converters (DACs), SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "adc-dac-data conversion",
    "wm8761cbged",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "wm8761cbged.kicad_sym",
    "wm8761cbged.kicad_mod",
    "wm8761cbged.glb",
    "wm8761cbged.step",
    "wm8761cbged.lbr",
    "docs/hero.png",
    "docs/wm8761cbged-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "wm8761cbged-hero.glb",
    "wm8761cbged-hero.overlay.json",
    "wm8761cbged-etched.glb"
  ],
  "component": {
    "mpn": "WM8761CBGED",
    "manufacturer": "Cirrus Logic",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/1b185dc6cd8fd7af591337208b97ab2b.pdf",
    "parts": {
      "symbol": "wm8761cbged.kicad_sym",
      "footprint": "wm8761cbged.kicad_mod",
      "model_3d": "wm8761cbged-hero.glb",
      "model_3d_plain": "wm8761cbged-etched.glb",
      "model_3d_step": "wm8761cbged-etched.step",
      "model_3d_step_plain": "wm8761cbged.step",
      "lbr": "wm8761cbged.lbr"
    },
    "distributor_links": {
      "lcsc": "C2667093",
      "digikey": "WM8761CBGED-ND",
      "mouser": "238-WM8761CBGED"
    },
    "distributor_check": {
      "checked_at": "2026-10-31T09:30:15Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "WM8761CBGED-ND",
        "status": "found",
        "lifecycle": "Obsolete"
      },
      "mouser": {
        "pn": "238-WM8761CBGED",
        "status": "found",
        "lifecycle": "Obsolete"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "LRCIN",
        "type": "input",
        "description": "Sample rate (left/right) clock input with Schmitt trigger buffer; an LRCIN of 4 BCKINs or less duration selects DSP format."
      },
      {
        "number": "2",
        "name": "DIN",
        "type": "input",
        "description": "Serial audio data input with Schmitt trigger buffer."
      },
      {
        "number": "3",
        "name": "BCKIN",
        "type": "input",
        "description": "Bit clock input with Schmitt trigger buffer; minimum cycle time 40ns."
      },
      {
        "number": "4",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection."
      },
      {
        "number": "5",
        "name": "CAP",
        "type": "passive",
        "description": "Analogue internal reference at VDD/2, to be decoupled with 10uF and 0.1uF capacitors."
      },
      {
        "number": "6",
        "name": "VOUTR",
        "type": "output",
        "description": "Right channel DAC output, 1.1 Vrms at 0dBFS into 10k load with VDD = 5V."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Negative supply (ground)."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply, 2.7V to 5.5V."
      },
      {
        "number": "9",
        "name": "VOUTL",
        "type": "output",
        "description": "Left channel DAC output, 1.1 Vrms at 0dBFS into 10k load with VDD = 5V."
      },
      {
        "number": "10",
        "name": "MUTE",
        "type": "bidirectional",
        "description": "Soft mute control with internal pull down: high = mute on, low = mute off, high impedance = automute (pin indicates automuted state through 10k)."
      },
      {
        "number": "11",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection."
      },
      {
        "number": "12",
        "name": "DEEMPH",
        "type": "input",
        "description": "De-emphasis select with internal pull up: high = de-emphasis on, low = off."
      },
      {
        "number": "13",
        "name": "FORMAT",
        "type": "input",
        "description": "Data input format select with internal pull up: low = 24-bit right justified or DSP 'late', high = 16-24-bit I2S or DSP 'early'."
      },
      {
        "number": "14",
        "name": "MCLK",
        "type": "input",
        "description": "Master clock input, 128fs to 768fs, max 50MHz; stopping MCLK powers the device down."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: MPN WM8761CBGED does not appear in this datasheet's ordering table (only WM8761CGED and WM8761CGED/R; CAP is described as 'Analogue output' but is a reference decoupling node that can optionally be driv; MUTE acts as input and as automute output, so it is classified bidirectional."
        ],
        "pages_sent": 23,
        "cost_usd": 0.1719,
        "at": "2026-10-31T09:30:05"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/1b185dc6cd8fd7af591337208b97ab2b.pdf",
        "pages": 23,
        "sha256": "dc529268faf1ead9",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "wm8761cbged.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "wm8761cbged-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "303047092f90b94fb57a28124545f5c3905fa6286faaf62f1b92d80522c49a6f",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ],
    "package_dims": {
      "package_code": "DM001.C",
      "source_page": 21,
      "D": {
        "nom_mm": 8.65,
        "range_mm": [
          8.55,
          8.75
        ]
      },
      "E1": {
        "nom_mm": 3.9,
        "range_mm": [
          3.8,
          4.0
        ]
      },
      "E": {
        "nom_mm": 6.0,
        "range_mm": [
          5.8,
          6.2
        ]
      },
      "e": {
        "nom_mm": 1.27,
        "range_mm": [
          null,
          null
        ]
      },
      "A": {
        "nom_mm": 1.55,
        "range_mm": [
          1.35,
          1.75
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "wm8761cbged.step",
        "verdict": "PASS",
        "reasons": [
          "height and body within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  }
}