WM8761CBGED from Cirrus Logic, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LRCIN	input	Sample rate (left/right) clock input with Schmitt trigger buffer; an LRCIN of 4 BCKINs or less duration selects DSP format.
2	DIN	input	Serial audio data input with Schmitt trigger buffer.
3	BCKIN	input	Bit clock input with Schmitt trigger buffer; minimum cycle time 40ns.
4	NC	unconnected	No internal connection.
5	CAP	passive	Analogue internal reference at VDD/2, to be decoupled with 10uF and 0.1uF capacitors.
6	VOUTR	output	Right channel DAC output, 1.1 Vrms at 0dBFS into 10k load with VDD = 5V.
7	GND	power_in	Negative supply (ground).
8	VDD	power_in	Positive supply, 2.7V to 5.5V.
9	VOUTL	output	Left channel DAC output, 1.1 Vrms at 0dBFS into 10k load with VDD = 5V.
10	MUTE	bidirectional	Soft mute control with internal pull down: high = mute on, low = mute off, high impedance = automute (pin indicates automuted state through 10k).
11	NC	unconnected	No internal connection.
12	DEEMPH	input	De-emphasis select with internal pull up: high = de-emphasis on, low = off.
13	FORMAT	input	Data input format select with internal pull up: low = 24-bit right justified or DSP 'late', high = 16-24-bit I2S or DSP 'early'.
14	MCLK	input	Master clock input, 128fs to 768fs, max 50MHz; stopping MCLK powers the device down.

Key specifications

Parameter	Value
Manufacturer	Cirrus Logic
Package	SOIC-14
Category	ADC/DAC/Data Conversion
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage		-0.3		7	V		5
Voltage range digital inputs		-0.3		0.3	V	GND -0.3V to VDD +0.3V (max printed as VDD +0.3V)	5
Master Clock Frequency				50	MHz		5
Operating temperature range	TA	-40		85	°C		5
Storage temperature after soldering		-65		150	°C		5
Supply range	VDD	2.7		5.5	V		6
Supply current			27		mA	VDD = 5V	6
Supply current			23		mA	VDD = 3.3V	6
Power down current			0.5		mA	VDD=3.3V	6
Input LOW level	VIL			0.8	V		6
Input HIGH level	VIH	2			V		6
SNR A-weighted	SNR	94	100		dB	A-weighted, @ fs = 48kHz	6
THD	THD		-90	-85	dB	1kHz, 0dBFs	6
Dynamic Range		90	100		dB	1kHz, THD+N @ -60dBFs	6
Gain mismatch channel-to-channel			1		%FSR	±1	7
Minimum resistance load		1			kΩ	To midrail or a.c. coupled	7
Maximum capacitance load				100	pF	5V or 3.3V	7
POR threshold			2.4		V		7
MCLK pulse width high	tMCLKH	8			ns		8
MCLK pulse width low	tMCLKL	8			ns		8
MCLK cycle time	tMCLKY	20			ns		8
BCKIN cycle time	tBCY	40			ns		8
BCKIN pulse width high	tBCH	16			ns		8
BCKIN pulse width low	tBCL	16			ns		8
LRCIN set-up time to BCKIN rising edge	tLRSU	8			ns		8
LRCIN hold time from BCKIN rising edge	tLRH	8			ns		8
DIN set-up time to BCKIN rising edge	tDS	8			ns		8
DIN hold time from BCKIN rising edge	tDH	8			ns		8

CAD (KiCad official)

Symbol: WM8761CBGED
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: wm8761cbged-etched.step / wm8761cbged-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); wm8761cbged.step / wm8761cbged.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cirrus Logic datasheet (23 pp, sha256 dc529268faf1ead9, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

WM8761CBGED

Verified WM8761CBGED

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README