component
WM8524CGEDT
Public Made by Adomby adom
Cirrus Logic Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "WM8524CGEDT",
"brief": "Cirrus Logic Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"manufacturer": "Cirrus Logic",
"package": "TSSOP-16",
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"category": "Data Converters",
"subcategory": "Digital To Analog Converters (DACs)",
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"digikey": "598-2458-ND",
"mouser": "238-WM8524CGEDT"
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"source": "Component Ocean /api/assign-pns",
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"number": "1",
"name": "LINEVOUTL",
"type": "output",
"description": "Left line output, specified at 2.1 Vrms typical at 0dBFS with a load impedance of 1 kΩ."
},
{
"number": "2",
"name": "CPVOUTN",
"type": "output",
"description": "Charge pump negative rail decoupling pin, generating the -3.3V ±10% rail used by the line driver."
},
{
"number": "3",
"name": "CPCB",
"type": "output",
"description": "Charge pump fly-back capacitor pin."
},
{
"number": "4",
"name": "LINEGND",
"type": "power_in",
"description": "Charge pump ground, with ground rail specified at 0 V."
},
{
"number": "5",
"name": "CPCA",
"type": "output",
"description": "Charge pump fly-back capacitor pin."
},
{
"number": "6",
"name": "LINEVDD",
"type": "power_in",
"description": "Charge pump supply, 3.3V ±10% (2.97 V to 3.63 V recommended), to be kept within 0.3 V of AVDD."
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{
"number": "7",
"name": "DACDAT",
"type": "input",
"description": "Digital audio interface data input (slave mode, left justified, right justified or I2S formats)."
},
{
"number": "8",
"name": "LRCLK",
"type": "input",
"description": "Digital audio interface left/right clock input, which must be synchronised with MCLK."
},
{
"number": "9",
"name": "BCLK",
"type": "input",
"description": "Digital audio interface bit clock input; the BCLK period must be greater than or equal to the MCLK period."
},
{
"number": "10",
"name": "MCLK",
"type": "input",
"description": "Master clock input supporting MCLK to LRCLK ratios of 128fs to 1152fs."
},
{
"number": "11",
"name": "MUTE",
"type": "input",
"description": "Active-low mute control: 0 applies mute with a softmute ramp over 800 samples, 1 gives normal operation (mute disabled)."
},
{
"number": "12",
"name": "AIFMODE",
"type": "input",
"description": "Tri-level audio interface format select: 0 = 24-bit left justified, 1 = 24-bit I2S, Z (left floating/open) = 24-bit right justified."
},
{
"number": "13",
"name": "AGND",
"type": "power_in",
"description": "Analogue ground, which must always be within 0.3 V of LINEGND."
},
{
"number": "14",
"name": "VMID",
"type": "output",
"description": "Analogue midrail decoupling pin, nominally 1.65V ±10%."
},
{
"number": "15",
"name": "AVDD",
"type": "power_in",
"description": "Analogue supply, 3.3V ±10% (2.97 V to 3.63 V recommended), to be kept within 0.3 V of LINEVDD."
},
{
"number": "16",
"name": "LINEVOUTR",
"type": "output",
"description": "Right line output, specified at 2.1 Vrms typical at 0dBFS with a load impedance of 1 kΩ."
}
],
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"primary_model": "claude-haiku-5-5",
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"guards": "pin_guards 0.1: passed",
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"extractor flagged: The pin configuration diagram on page 3 is graphic and not present in the extracted text. Pin number; The datasheet lists AIFMODE as tri-level (0 / 1 / Z) and does not assign a KiCad class; it is typed ; Pin types are mapped to KiCad ERC classes from the datasheet's Type column: Analogue Out is output, "
],
"pages_sent": 25,
"cost_usd": 0.0731,
"at": "2026-10-30T17:47:28"
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"pages": 25,
"sha256": "f4e0e80e8ae304b6",
"source_tier": "lcsc"
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"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
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"seat": "z = 0",
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],
"package_dims": {
"package_code": "DT (16 PIN TSSOP, DM013.B)",
"source_page": 23,
"D": {
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"E1": {
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"metadata": {
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"Package": "TSSOP-16",
"Category": "Data Converters",
"Pins": "16"
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{
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"source": "datasheet"
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{
"name": "Voltage range digital inputs",
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{
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{
"name": "Temperature range",
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{
"name": "Storage temperature after soldering",
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{
"name": "Output Level",
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"kind": "electrical",
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"min": 1.89,
"typ": 2.1,
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"source_page": 6,
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{
"name": "DC Offset at LINEVOUTL and LINEVOUTR",
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"min": -1,
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{
"name": "Input Leakage",
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"min": -0.9,
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{
"name": "VDD level to POR rising edge (VMID rising)",
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"min": 0.63,
"typ": 0.8,
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{
"name": "VDD level to POR rising edge (LINEVDD/AVDD rising)",
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{
"name": "VDD level to POR falling edge (LINEVDD/AVDD falling)",
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"unit": "V",
"min": 0.96,
"typ": 1.46,
"max": 1.97,
"conditions": "Measured from LINEGND",
"source_page": 11,
"source": "datasheet"
},
{
"name": "MCLK cycle time",
"symbol": "tMCLKY",
"kind": "timing",
"unit": "ns",
"min": 27,
"typ": null,
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"conditions": "LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C",
"source_page": 8,
"source": "datasheet"
}
]
}
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"email": "[email protected]"
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