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WM8524CGEDT

Cirrus Logic · Digital To Analog Converters (DACs) · TSSOP-16

WM8524CGEDT from Cirrus Logic, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LINEVOUTL output Left line output, specified at 2.1 Vrms typical at 0dBFS with a load impedance of 1 kΩ.
2 CPVOUTN output Charge pump negative rail decoupling pin, generating the -3.3V ±10% rail used by the line driver.
3 CPCB output Charge pump fly-back capacitor pin.
4 LINEGND power_in Charge pump ground, with ground rail specified at 0 V.
5 CPCA output Charge pump fly-back capacitor pin.
6 LINEVDD power_in Charge pump supply, 3.3V ±10% (2.97 V to 3.63 V recommended), to be kept within 0.3 V of AVDD.
7 DACDAT input Digital audio interface data input (slave mode, left justified, right justified or I2S formats).
8 LRCLK input Digital audio interface left/right clock input, which must be synchronised with MCLK.
9 BCLK input Digital audio interface bit clock input; the BCLK period must be greater than or equal to the MCLK period.
10 MCLK input Master clock input supporting MCLK to LRCLK ratios of 128fs to 1152fs.
11 MUTE input Active-low mute control: 0 applies mute with a softmute ramp over 800 samples, 1 gives normal operation (mute disabled).
12 AIFMODE input Tri-level audio interface format select: 0 = 24-bit left justified, 1 = 24-bit I2S, Z (left floating/open) = 24-bit right justified.
13 AGND power_in Analogue ground, which must always be within 0.3 V of LINEGND.
14 VMID output Analogue midrail decoupling pin, nominally 1.65V ±10%.
15 AVDD power_in Analogue supply, 3.3V ±10% (2.97 V to 3.63 V recommended), to be kept within 0.3 V of LINEVDD.
16 LINEVOUTR output Right line output, specified at 2.1 Vrms typical at 0dBFS with a load impedance of 1 kΩ.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package TSSOP-16
Category Data Converters
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analogue supply range AVDD, LINEVDD 2.97 3.3 3.63 V 5
Supply voltage (absolute maximum) AVDD, LINEVDD -0.3 4.5 V 5
Voltage range digital inputs -0.3 0.3 V Min: LINEGND -0.3V; max: LINEVDD +0.3V 5
Voltage range analogue inputs -0.3 0.3 V Min: AGND -0.3V; max: AVDD +0.3V 5
Temperature range TA -40 125 °C 5
Storage temperature after soldering -65 150 °C 5
Operating temperature range TA -40 85 °C 1
Output Level 1.89 2.1 2.31 Vrms 0dBFS 6
DC Offset at LINEVOUTL and LINEVOUTR -1 0 1 mV 6
Input Leakage -0.9 0.9 A 6
VDD level to POR rising edge (VMID rising) Vpord_hi 0.63 0.8 1 V Measured from LINEGND 11
VDD level to POR rising edge (LINEVDD/AVDD rising) Vpora_hi 1.44 1.8 2.18 V Measured from LINEGND 11
VDD level to POR falling edge (LINEVDD/AVDD falling) Vpora_lo 0.96 1.46 1.97 V Measured from LINEGND 11
MCLK cycle time tMCLKY 27 500 ns LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C 8

CAD (KiCad official)

  • Symbol: WM8524CGEDT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: wm8524cgedt-etched.step / wm8524cgedt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); wm8524cgedt.step / wm8524cgedt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (25 pp, sha256 f4e0e80e8ae304b6, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF