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VSP5610RSHR

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Texas Instruments Analog Front End (AFE), VQFN-56(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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VSP5610RSHR

Texas Instruments · Analog Front End (AFE) · VQFN-56(7x7)

VSP5610RSHR from Texas Instruments, in a VQFN-56(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TEST input Internal test pin; connect to DGND
2 AVDD_LDO power_out Analog core power voltage output; not connected, open
3 VSS power_in LDO and analog I/O ground
4 AIN1 input First channel analog signal input
5 AINGND1 power_in First channel analog signal ground
6 AIN2 input Second channel analog signal input
7 AINGND2 power_in Second channel analog signal ground
8 AIN3 input Third channel analog signal input
9 AINGND3 power_in Third channel analog signal ground
10 AIN4 input Fourth channel analog signal input
11 AINGND4 power_in Fourth channel analog signal ground
12 VSS power_in LDO and analog I/O ground
13 REF_AIN bidirectional Analog signal reference output (default) or analog signal reference input
14 ISET output Internal reference voltage output; bypass to ground with a 10-kΩ ±1% resistor
15 VSS power_in LDO and analog I/O ground
16 REFP output Positive reference; bypass to AGND with a 0.1-μF capacitor
17 REFN output Negative reference; bypass to AGND with a 0.1-μF capacitor
18 VSS power_in LDO and analog I/O ground
19 VDD power_in LDO and analog I/O power supply
20 XSH1 output Sensor shift gate output 1
21 XSH2 output Sensor shift gate output 2
22 XSH3 output Sensor shift gate output 3
23 XSH4 output Sensor shift gate output 4
24 GPIO0 bidirectional General-purpose input port 0 (default, with internal pull-down) or general-purpose output port 0
25 SDO/GPIO2 bidirectional General-purpose input port 2 (default, with internal pull-down), general-purpose output port 2, or serial I/F data output
26 DVSS power_in Digital ground
27 RCLKN input LVDS clock input
28 RCLKP input CMOS master clock input or positive LVDS clock input
29 DVSS power_in Digital ground
30 SEN input Serial I/F enable; active low with internal pull-up resistor
31 SDI bidirectional Serial I/F data input or serial I/F data input/output with internal pull-down resistor
32 SCLK input Serial I/F clock with internal pull-down resistor
33 TCLK-/CK1/D7 output Negative LVDS clock output or clock output 1 or data output bit 7
34 TCLK+/CK0/D6 output Positive LVDS clock output or clock output 0 or data output bit 6
35 TC-/D5 output Negative TC channel LVDS data output or data output bit 5
36 TC+/D4 output Positive TC channel LVDS data output or data output bit 4
37 TB-/D3 output Negative TB channel LVDS data output or data output bit 3
38 TB+/D2 output Positive TB channel LVDS data output or data output bit 2
39 TA-/D1 output Negative TA channel LVDS data output or data output bit 1
40 TA+/D0 output Positive TA channel LVDS data output or data output bit 0
41 LVDD power_in LVDS/CMOS output power supply
42 LVSS power_in LVDS/CMOS output ground
43 DVDD_IO power_in Digital I/O power supply
44 DVSS power_in Digital ground
45 XLSYNC bidirectional Internal line synchronous signal output (default, with internal pull-down) or external line synchronous signal input
46 SDO/GPIO1 bidirectional General-purpose input port 1 (default, with internal pull-down), general-purpose output port 1, or serial I/F data output
47 XST/GPIO3 bidirectional General-purpose input port 3 (default, with internal pull-down), general-purpose output port 3, or XST storage pulse output
48 XCLR output Sensor clear gate output
49 XP1 output Fast transfer clock output φ1
50 XP2 output Fast transfer clock output φ2
51 XP3 output Fast transfer clock output φ3
52 XP4 output Fast transfer clock output φ4
53 X1L output Fast transfer clock output 1L
54 X2L output Fast transfer clock output 2L
55 XCP output Clamp gate clock output
56 XRS output Reset gate clock output
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-56(7x7)
Category Data Acquisition
Pins 57

CAD (KiCad official)

  • Symbol: VSP5610RSHR
  • Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
  • 3D model: VQFN-56(7x7) (KiCad packages3D, STEP)
  • 3D model files: vsp5610rshr-etched.step / vsp5610rshr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vsp5610rshr.step / vsp5610rshr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 b01183c0d2c944e8, retrieved 2026-10-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF