component
VSP5610RSHR
Public Made by Adomby adom
Texas Instruments Analog Front End (AFE), VQFN-56(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+94@@ -0,0 +1,94 @@+# VSP5610RSHR++**Texas Instruments** · Analog Front End (AFE) · VQFN-56(7x7)++VSP5610RSHR from Texas Instruments, in a VQFN-56(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TEST | input | Internal test pin; connect to DGND |+| 2 | AVDD_LDO | power_out | Analog core power voltage output; not connected, open |+| 3 | VSS | power_in | LDO and analog I/O ground |+| 4 | AIN1 | input | First channel analog signal input |+| 5 | AINGND1 | power_in | First channel analog signal ground |+| 6 | AIN2 | input | Second channel analog signal input |+| 7 | AINGND2 | power_in | Second channel analog signal ground |+| 8 | AIN3 | input | Third channel analog signal input |+| 9 | AINGND3 | power_in | Third channel analog signal ground |+| 10 | AIN4 | input | Fourth channel analog signal input |+| 11 | AINGND4 | power_in | Fourth channel analog signal ground |+| 12 | VSS | power_in | LDO and analog I/O ground |+| 13 | REF_AIN | bidirectional | Analog signal reference output (default) or analog signal reference input |+| 14 | ISET | output | Internal reference voltage output; bypass to ground with a 10-kΩ ±1% resistor |+| 15 | VSS | power_in | LDO and analog I/O ground |+| 16 | REFP | output | Positive reference; bypass to AGND with a 0.1-μF capacitor |+| 17 | REFN | output | Negative reference; bypass to AGND with a 0.1-μF capacitor |+| 18 | VSS | power_in | LDO and analog I/O ground |+| 19 | VDD | power_in | LDO and analog I/O power supply |+| 20 | XSH1 | output | Sensor shift gate output 1 |+| 21 | XSH2 | output | Sensor shift gate output 2 |+| 22 | XSH3 | output | Sensor shift gate output 3 |+| 23 | XSH4 | output | Sensor shift gate output 4 |+| 24 | GPIO0 | bidirectional | General-purpose input port 0 (default, with internal pull-down) or general-purpose output port 0 |+| 25 | SDO/GPIO2 | bidirectional | General-purpose input port 2 (default, with internal pull-down), general-purpose output port 2, or serial I/F data output |+| 26 | DVSS | power_in | Digital ground |+| 27 | RCLKN | input | LVDS clock input |+| 28 | RCLKP | input | CMOS master clock input or positive LVDS clock input |+| 29 | DVSS | power_in | Digital ground |+| 30 | SEN | input | Serial I/F enable; active low with internal pull-up resistor |+| 31 | SDI | bidirectional | Serial I/F data input or serial I/F data input/output with internal pull-down resistor |+| 32 | SCLK | input | Serial I/F clock with internal pull-down resistor |+| 33 | TCLK-/CK1/D7 | output | Negative LVDS clock output or clock output 1 or data output bit 7 |+| 34 | TCLK+/CK0/D6 | output | Positive LVDS clock output or clock output 0 or data output bit 6 |+| 35 | TC-/D5 | output | Negative TC channel LVDS data output or data output bit 5 |+| 36 | TC+/D4 | output | Positive TC channel LVDS data output or data output bit 4 |+| 37 | TB-/D3 | output | Negative TB channel LVDS data output or data output bit 3 |+| 38 | TB+/D2 | output | Positive TB channel LVDS data output or data output bit 2 |+| 39 | TA-/D1 | output | Negative TA channel LVDS data output or data output bit 1 |+| 40 | TA+/D0 | output | Positive TA channel LVDS data output or data output bit 0 |+| 41 | LVDD | power_in | LVDS/CMOS output power supply |+| 42 | LVSS | power_in | LVDS/CMOS output ground |+| 43 | DVDD_IO | power_in | Digital I/O power supply |+| 44 | DVSS | power_in | Digital ground |+| 45 | XLSYNC | bidirectional | Internal line synchronous signal output (default, with internal pull-down) or external line synchronous signal input |+| 46 | SDO/GPIO1 | bidirectional | General-purpose input port 1 (default, with internal pull-down), general-purpose output port 1, or serial I/F data output |+| 47 | XST/GPIO3 | bidirectional | General-purpose input port 3 (default, with internal pull-down), general-purpose output port 3, or XST storage pulse output |+| 48 | XCLR | output | Sensor clear gate output |+| 49 | XP1 | output | Fast transfer clock output φ1 |+| 50 | XP2 | output | Fast transfer clock output φ2 |+| 51 | XP3 | output | Fast transfer clock output φ3 |+| 52 | XP4 | output | Fast transfer clock output φ4 |+| 53 | X1L | output | Fast transfer clock output 1L |+| 54 | X2L | output | Fast transfer clock output 2L |+| 55 | XCP | output | Clamp gate clock output |+| 56 | XRS | output | Reset gate clock output |+| 57 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-56(7x7) |+| Category | Data Acquisition |+| Pins | 57 |++## CAD (KiCad official)++- Symbol: `VSP5610RSHR`+- Footprint: `Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm`+- 3D model: VQFN-56(7x7) (KiCad packages3D, STEP)+- 3D model files: `vsp5610rshr-etched.step` / `vsp5610rshr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vsp5610rshr.step` / `vsp5610rshr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/vsp5612) (47 pp, sha256 `b01183c0d2c944e8`, retrieved 2026-10-05, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/vsp5610rshr-datasheet.pdf)
page.jsonadded+454@@ -0,0 +1,454 @@+{+ "slug": "vsp5610rshr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog Front End (AFE), VQFN-56(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "vsp5610rshr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "vsp5610rshr.kicad_sym",+ "vsp5610rshr.kicad_mod",+ "vsp5610rshr.glb",+ "vsp5610rshr.step",+ "vsp5610rshr.lbr",+ "docs/hero.png",+ "docs/vsp5610rshr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "vsp5610rshr-hero.glb",+ "vsp5610rshr-hero.overlay.json"+ ],+ "component": {+ "mpn": "VSP5610RSHR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-56(7x7)",+ "pin_count": 57,+ "category": "Data Acquisition",+ "subcategory": "Analog Front End (AFE)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/vsp5612",+ "parts": {+ "symbol": "vsp5610rshr.kicad_sym",+ "footprint": "vsp5610rshr.kicad_mod",+ "model_3d": "vsp5610rshr-hero.glb",+ "model_3d_plain": "vsp5610rshr.glb",+ "model_3d_step": "vsp5610rshr-etched.step",+ "model_3d_step_plain": "vsp5610rshr.step",+ "lbr": "vsp5610rshr.lbr"+ },+ "distributor_links": {+ "lcsc": 2651566,+ "digikey": "296-29456-2-ND",+ "mouser": "595-VSP5610RSHR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T20:10:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-29456-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-VSP5610RSHR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "TEST",+ "type": "input",+ "description": "Internal test pin; connect to DGND"+ },+ {+ "number": "2",+ "name": "AVDD_LDO",+ "type": "power_out",+ "description": "Analog core power voltage output; not connected, open"+ },+ {+ "number": "3",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "4",+ "name": "AIN1",+ "type": "input",+ "description": "First channel analog signal input"+ },+ {+ "number": "5",+ "name": "AINGND1",+ "type": "power_in",+ "description": "First channel analog signal ground"+ },+ {+ "number": "6",+ "name": "AIN2",+ "type": "input",+ "description": "Second channel analog signal input"+ },+ {+ "number": "7",+ "name": "AINGND2",+ "type": "power_in",+ "description": "Second channel analog signal ground"+ },+ {+ "number": "8",+ "name": "AIN3",+ "type": "input",+ "description": "Third channel analog signal input"+ },+ {+ "number": "9",+ "name": "AINGND3",+ "type": "power_in",+ "description": "Third channel analog signal ground"+ },+ {+ "number": "10",+ "name": "AIN4",+ "type": "input",+ "description": "Fourth channel analog signal input"+ },+ {+ "number": "11",+ "name": "AINGND4",+ "type": "power_in",+ "description": "Fourth channel analog signal ground"+ },+ {+ "number": "12",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "13",+ "name": "REF_AIN",+ "type": "bidirectional",+ "description": "Analog signal reference output (default) or analog signal reference input"+ },+ {+ "number": "14",+ "name": "ISET",+ "type": "output",+ "description": "Internal reference voltage output; bypass to ground with a 10-kΩ ±1% resistor"+ },+ {+ "number": "15",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "16",+ "name": "REFP",+ "type": "output",+ "description": "Positive reference; bypass to AGND with a 0.1-μF capacitor"+ },+ {+ "number": "17",+ "name": "REFN",+ "type": "output",+ "description": "Negative reference; bypass to AGND with a 0.1-μF capacitor"+ },+ {+ "number": "18",+ "name": "VSS",+ "type": "power_in",+ "description": "LDO and analog I/O ground"+ },+ {+ "number": "19",+ "name": "VDD",+ "type": "power_in",+ "description": "LDO and analog I/O power supply"+ },+ {+ "number": "20",+ "name": "XSH1",+ "type": "output",+ "description": "Sensor shift gate output 1"+ },+ {+ "number": "21",+ "name": "XSH2",+ "type": "output",+ "description": "Sensor shift gate output 2"+ },+ {+ "number": "22",+ "name": "XSH3",+ "type": "output",+ "description": "Sensor shift gate output 3"+ },+ {+ "number": "23",+ "name": "XSH4",+ "type": "output",+ "description": "Sensor shift gate output 4"+ },+ {+ "number": "24",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose input port 0 (default, with internal pull-down) or general-purpose output port 0"+ },+ {+ "number": "25",+ "name": "SDO/GPIO2",+ "type": "bidirectional",+ "description": "General-purpose input port 2 (default, with internal pull-down), general-purpose output port 2, or serial I/F data output"+ },+ {+ "number": "26",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground"+ },+ {+ "number": "27",+ "name": "RCLKN",+ "type": "input",+ "description": "LVDS clock input"+ },+ {+ "number": "28",+ "name": "RCLKP",+ "type": "input",+ "description": "CMOS master clock input or positive LVDS clock input"+ },+ {+ "number": "29",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground"+ },+ {+ "number": "30",+ "name": "SEN",+ "type": "input",+ "description": "Serial I/F enable; active low with internal pull-up resistor"+ },+ {+ "number": "31",+ "name": "SDI",+ "type": "bidirectional",+ "description": "Serial I/F data input or serial I/F data input/output with internal pull-down resistor"+ },+ {+ "number": "32",+ "name": "SCLK",+ "type": "input",+ "description": "Serial I/F clock with internal pull-down resistor"+ },+ {+ "number": "33",+ "name": "TCLK–/CK1/D7",+ "type": "output",+ "description": "Negative LVDS clock output or clock output 1 or data output bit 7"+ },+ {+ "number": "34",+ "name": "TCLK+/CK0/D6",+ "type": "output",+ "description": "Positive LVDS clock output or clock output 0 or data output bit 6"+ },+ {+ "number": "35",+ "name": "TC–/D5",+ "type": "output",+ "description": "Negative TC channel LVDS data output or data output bit 5"+ },+ {+ "number": "36",+ "name": "TC+/D4",+ "type": "output",+ "description": "Positive TC channel LVDS data output or data output bit 4"+ },+ {+ "number": "37",+ "name": "TB–/D3",+ "type": "output",+ "description": "Negative TB channel LVDS data output or data output bit 3"+ },+ {+ "number": "38",+ "name": "TB+/D2",+ "type": "output",+ "description": "Positive TB channel LVDS data output or data output bit 2"+ },+ {+ "number": "39",+ "name": "TA–/D1",+ "type": "output",+ "description": "Negative TA channel LVDS data output or data output bit 1"+ },+ {+ "number": "40",+ "name": "TA+/D0",+ "type": "output",+ "description": "Positive TA channel LVDS data output or data output bit 0"+ },+ {+ "number": "41",+ "name": "LVDD",+ "type": "power_in",+ "description": "LVDS/CMOS output power supply"+ },+ {+ "number": "42",+ "name": "LVSS",+ "type": "power_in",+ "description": "LVDS/CMOS output ground"+ },+ {+ "number": "43",+ "name": "DVDD_IO",+ "type": "power_in",+ "description": "Digital I/O power supply"+ },+ {+ "number": "44",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground"+ },+ {+ "number": "45",+ "name": "XLSYNC",+ "type": "bidirectional",+ "description": "Internal line synchronous signal output (default, with internal pull-down) or external line synchronous signal input"+ },+ {+ "number": "46",+ "name": "SDO/GPIO1",+ "type": "bidirectional",+ "description": "General-purpose input port 1 (default, with internal pull-down), general-purpose output port 1, or serial I/F data output"+ },+ {+ "number": "47",+ "name": "XST/GPIO3",+ "type": "bidirectional",+ "description": "General-purpose input port 3 (default, with internal pull-down), general-purpose output port 3, or XST storage pulse output"+ },+ {+ "number": "48",+ "name": "XCLR",+ "type": "output",+ "description": "Sensor clear gate output"+ },+ {+ "number": "49",+ "name": "XP1",+ "type": "output",+ "description": "Fast transfer clock output φ1"+ },+ {+ "number": "50",+ "name": "XP2",+ "type": "output",+ "description": "Fast transfer clock output φ2"+ },+ {+ "number": "51",+ "name": "XP3",+ "type": "output",+ "description": "Fast transfer clock output φ3"+ },+ {+ "number": "52",+ "name": "XP4",+ "type": "output",+ "description": "Fast transfer clock output φ4"+ },+ {+ "number": "53",+ "name": "X1L",+ "type": "output",+ "description": "Fast transfer clock output 1L"+ },+ {+ "number": "54",+ "name": "X2L",+ "type": "output",+ "description": "Fast transfer clock output 2L"+ },+ {+ "number": "55",+ "name": "XCP",+ "type": "output",+ "description": "Clamp gate clock output"+ },+ {+ "number": "56",+ "name": "XRS",+ "type": "output",+ "description": "Reset gate clock output"+ },+ {+ "number": "57",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 57 added from the footprint"+ ],+ "pages_sent": 14,+ "cost_usd": 0.2103,+ "at": "2026-10-05T20:10:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/vsp5612",+ "pages": 47,+ "sha256": "b01183c0d2c944e8",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 57,+ "described": 57,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}