# VS3618AS

**Vergiga(威兆)** · IC · SOP-8

VS3618AS from Vergiga(威兆), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the N-channel MOSFET (pins 1-3 are source); pin 1 is marked by the pin 1 index. |
| 2 | S | passive | Source of the N-channel MOSFET, connected with pins 1 and 3. |
| 3 | S | passive | Source of the N-channel MOSFET, connected with pins 1 and 2. |
| 4 | G | input | Gate of the N-channel MOSFET with 5V logic-level control; VGS rated ±20 V. |
| 5 | D | passive | Drain of the MOSFET (pins 5-8 are drain); VDS rated 30 V. |
| 6 | D | passive | Drain of the MOSFET, connected with pins 5, 7 and 8. |
| 7 | D | passive | Drain of the MOSFET, connected with pins 5, 6 and 8. |
| 8 | D | passive | Drain of the MOSFET, connected with pins 5, 6 and 7. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Vergiga(威兆) |
| Package | SOP-8 |
| Category |  |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source breakdown voltage | V(BR)DSS | 30 |  |  | V | VGS=0V, ID=250μA, Tj=25°C | 2 |
| Zero gate voltage drain current | IDSS |  |  | 1 | uA | VDS=30V, VGS=0V, Tj=25°C | 2 |
| Zero gate voltage drain current (Tj=125°C) | IDSS |  |  | 100 | uA | VDS=30V, VGS=0V, Tj=125°C | 2 |
| Gate-body leakage current | IGSS | -100 |  | 100 | nA | VGS=±20V, VDS=0V, Tj=25°C | 2 |
| Gate threshold voltage | VGS(TH) | 1.3 | 1.9 | 2.4 | V | VDS=VGS, ID=250μA, Tj=25°C | 2 |
| Drain-source on-state resistance | RDS(ON) |  | 6.6 | 9 | mΩ | VGS=10V, ID=8A, Tj=25°C; pulse width ≤300μs, duty cycle ≤2% | 2 |
| Drain-source on-state resistance | RDS(ON) |  | 9.6 | 13 | mΩ | VGS=4.5V, ID=4A, Tj=25°C; pulse width ≤300μs, duty cycle ≤2% | 2 |
| Forward on voltage | VSD |  | 0.8 | 1.2 | V | ISD=8A, VGS=0V, Tj=25°C | 2 |
| Gate-source voltage | VGS | -20 |  | 20 | V |  | 1 |
| Diode continuous forward current | IS |  |  | 2.6 | A | TA=25°C | 1 |
| Continuous drain current | ID |  |  | 16 | A | VGS=10V, TA=25°C | 1 |
| Continuous drain current | ID |  |  | 10 | A | VGS=10V, TA=100°C | 1 |
| Pulse drain current | IDM |  |  | 64 | A | TA=25°C, repetitive rating; pulse width limited by max junction temperature (note 1) | 1 |
| Avalanche energy, single pulsed | EAS |  |  | 25 | mJ | Limited by TJmax, starting TJ=25°C, L=0.5mH, RG=25Ω, IAS=10A, VGS=10V (note 2) | 1 |
| Maximum power dissipation | PD |  |  | 3.1 | W | TA=25°C | 1 |
| Storage and junction temperature range | TSTG ,TJ | -55 |  | 150 | °C |  | 1 |
| Thermal resistance, junction-to-lead | RθJL |  | 24 |  | °C/W |  | 1 |
| Thermal resistance, junction-to-ambient | RJA |  | 40 |  | °C/W |  | 1 |

## CAD (KiCad official)

- Symbol: `VS3618AS`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `vs3618as-etched.step` / `vs3618as-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vs3618as.step` / `vs3618as.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Vergiga(威兆) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603034843206721536) (6 pp, sha256 `88749cfa08fa8257`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/vs3618as-datasheet.pdf)