component
VS3508AS
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Vergiga(威兆) , SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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VS3508AS
Vergiga(威兆) · IC · SOP-8
VS3508AS from Vergiga(威兆), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied with pins 2 and 3 (Source Pin1-3); drain-source breakdown voltage -30 V. |
| 2 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 3 (Source Pin1-3); continuous drain current -13 A at TA=25°C. |
| 3 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 2 (Source Pin1-3); diode continuous forward current -3 A. |
| 4 | G | input | Gate of the P-channel MOSFET (Gate Pin4); gate-source voltage rated ±20 V with threshold -1.0 to -2.5 V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied with pins 6-8 (Drain Pin 5-8); pulsed drain current -52 A. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 7 and 8 (Drain Pin 5-8); drain-source breakdown voltage -30 V. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 6 and 8 (Drain Pin 5-8); RDS(on) typ 8.5 mΩ at VGS=-10 V. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied with pins 5-7 (Drain Pin 5-8); RDS(on) typ 15 mΩ at VGS=-4.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vergiga(威兆) |
| Package | SOP-8 |
| Category | |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | V(BR)DSS | -30 | V | VGS=0V ID=-250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -1 | μA | VDS=-30V,VGS=0V | 2 | ||
| Zero Gate Voltage Drain Current (Tj=125℃) | IDSS | -100 | μA | VDS=-30V,VGS=0V | 2 | ||
| Gate-Body Leakage Current | IGSS | -100 | 100 | nA | VGS=±20V,VDS=0V | 2 | |
| Gate Threshold Voltage | VGS(TH) | -1 | -1.8 | -2.5 | V | VDS=VGS,ID=-250μA | 2 |
| Drain-Source On-State Resistance | RDS(ON) | 8.5 | 10 | mΩ | VGS=-10V, ID=-10A | 2 | |
| Drain-Source On-State Resistance | RDS(ON) | 15 | 18 | mΩ | VGS=-4.5V, ID=-6A | 2 | |
| Forward on voltage | VSD | -0.83 | -1.2 | V | ISD=-10A,VGS=0V | 2 | |
| Continuous drain current @ TA=25°C (VGS=-10V) | ID | -13 | A | VGS=-10V, TA=25°C | 1 | ||
| Continuous drain current @ TA=100°C (VGS=-10V) | ID | -8.5 | A | VGS=-10V, TA=100°C | 1 | ||
| Pulse drain current | IDM | -52 | A | TA=25°C, tested ① | 1 | ||
| Diode continuous forward current | IS | -3 | A | TA=25°C | 1 | ||
| Avalanche energy, single pulsed | EAS | 81 | mJ | ② | 1 | ||
| Maximum power dissipation | PD | 3.1 | W | TA=25°C | 1 | ||
| Gate-Source voltage | VGS | -20 | 20 | V | 1 | ||
| Storage and operating temperature range | TSTG/TJ | -55 | 150 | °C | 1 | ||
| Thermal Resistance-Junction to Lead | RθJL | 24 | °C/W | 1 | |||
| Thermal Resistance-Junction to Ambient | RθJA | 40 | °C/W | 1 |
CAD (KiCad official)
- Symbol:
VS3508AS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
vs3508as-etched.step/vs3508as-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vs3508as.step/vs3508as.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vergiga(威兆) datasheet (6 pp, sha256
0986decd092a589e, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# VS3508AS
**Vergiga(威兆)** · IC · SOP-8
VS3508AS from Vergiga(威兆), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied with pins 2 and 3 (Source Pin1-3); drain-source breakdown voltage -30 V. |
| 2 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 3 (Source Pin1-3); continuous drain current -13 A at TA=25°C. |
| 3 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 2 (Source Pin1-3); diode continuous forward current -3 A. |
| 4 | G | input | Gate of the P-channel MOSFET (Gate Pin4); gate-source voltage rated ±20 V with threshold -1.0 to -2.5 V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied with pins 6-8 (Drain Pin 5-8); pulsed drain current -52 A. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 7 and 8 (Drain Pin 5-8); drain-source breakdown voltage -30 V. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 6 and 8 (Drain Pin 5-8); RDS(on) typ 8.5 mΩ at VGS=-10 V. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied with pins 5-7 (Drain Pin 5-8); RDS(on) typ 15 mΩ at VGS=-4.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vergiga(威兆) |
| Package | SOP-8 |
| Category | |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | V(BR)DSS | -30 | | | V | VGS=0V ID=-250μA | 2 |
| Zero Gate Voltage Drain Current | IDSS | | | -1 | μA | VDS=-30V,VGS=0V | 2 |
| Zero Gate Voltage Drain Current (Tj=125℃) | IDSS | | | -100 | μA | VDS=-30V,VGS=0V | 2 |
| Gate-Body Leakage Current | IGSS | -100 | | 100 | nA | VGS=±20V,VDS=0V | 2 |
| Gate Threshold Voltage | VGS(TH) | -1 | -1.8 | -2.5 | V | VDS=VGS,ID=-250μA | 2 |
| Drain-Source On-State Resistance | RDS(ON) | | 8.5 | 10 | mΩ | VGS=-10V, ID=-10A | 2 |
| Drain-Source On-State Resistance | RDS(ON) | | 15 | 18 | mΩ | VGS=-4.5V, ID=-6A | 2 |
| Forward on voltage | VSD | | -0.83 | -1.2 | V | ISD=-10A,VGS=0V | 2 |
| Continuous drain current @ TA=25°C (VGS=-10V) | ID | -13 | | | A | VGS=-10V, TA=25°C | 1 |
| Continuous drain current @ TA=100°C (VGS=-10V) | ID | -8.5 | | | A | VGS=-10V, TA=100°C | 1 |
| Pulse drain current | IDM | -52 | | | A | TA=25°C, tested ① | 1 |
| Diode continuous forward current | IS | -3 | | | A | TA=25°C | 1 |
| Avalanche energy, single pulsed | EAS | | | 81 | mJ | ② | 1 |
| Maximum power dissipation | PD | | | 3.1 | W | TA=25°C | 1 |
| Gate-Source voltage | VGS | -20 | | 20 | V | | 1 |
| Storage and operating temperature range | TSTG/TJ | -55 | | 150 | °C | | 1 |
| Thermal Resistance-Junction to Lead | RθJL | | 24 | | °C/W | | 1 |
| Thermal Resistance-Junction to Ambient | RθJA | | 40 | | °C/W | | 1 |
## CAD (KiCad official)
- Symbol: `VS3508AS`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `vs3508as-etched.step` / `vs3508as-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `vs3508as.step` / `vs3508as.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vergiga(威兆) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603034853831434240) (6 pp, sha256 `0986decd092a589e`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/vs3508as-datasheet.pdf)