component
VS-25TTS12-M3
Public Made by Adomby adom
Vishay Intertech Thyristors (SCR)/Modules, TO-220AB-3. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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VS-25TTS12-M3
Vishay Intertech · Thyristors (SCR)/Modules · TO-220AB-3
VS-25TTS12-M3 from Vishay Intertech, in a TO-220AB-3. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K | passive | Cathode of the single SCR, labeled (K) in the circuit configuration; this variant is rated for 1200 V VRRM and VDRM. |
| 2 | A | passive | Anode of the single SCR, labeled (A) in the circuit configuration; maximum on-state RMS current is 25 A and average on-state current is 16 A at TC = 93 °C. |
| 3 | G | input | Gate of the SCR, labeled (G); limits are 8.0 W peak gate power, 2.0 W average gate power, 1.5 A peak positive gate current, 10 V peak negative gate voltage, and 45 mA maximum DC gate current to trigger at TJ = 25 °C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | TO-220AB-3 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Repetitive peak reverse voltage (VRRM, 1200 V part) | VRRM | 1200 | V | 1 | |||
| Repetitive peak off-state voltage (VDRM, 1200 V part) | VDRM | 1200 | V | 1 | |||
| Maximum average on-state current | IT(AV) | 16 | A | TC = 93 °C, 180° conduction half sine wave | 2 | ||
| Maximum RMS on-state current | IRMS | 25 | A | 2 | |||
| Maximum peak one-cycle non-repetitive surge current | ITSM | 270 | A | 10 ms sine pulse, rated VRRM applied | 2 | ||
| Maximum peak one-cycle non-repetitive surge current | ITSM | 320 | A | 10 ms sine pulse, no voltage reapplied | 2 | ||
| Maximum I2t for fusing | I2t | 365 | A2s | 10 ms sine pulse, rated VRRM applied | 2 | ||
| Maximum I2t for fusing | I2t | 515 | A2s | 10 ms sine pulse, no voltage reapplied | 2 | ||
| Maximum I2t for fusing | I2t | 5152 | A2s | t = 0.1 to 10 ms, no voltage reapplied | 2 | ||
| Maximum on-state voltage drop | VTM | 1.25 | V | 16 A, TJ = 25 °C | 2 | ||
| On-state slope resistance | rt | 12 | mΩ | TJ = 125 °C | 2 | ||
| Threshold voltage | VT(TO) | 1 | V | 2 | |||
| Maximum reverse and direct leakage current | IRM/IDM | 0.5 | mA | TJ = 25 °C, VR = Rated VRRM/VDRM | 2 | ||
| Maximum reverse and direct leakage current | IRM/IDM | 10 | mA | TJ = 125 °C, VR = Rated VRRM/VDRM | 2 | ||
| Holding current | IH | 150 | mA | Anode supply = 6 V, resistive load, initial IT = 1 A, TJ = 25 °C | 2 | ||
| Maximum latching current | IL | 200 | mA | Anode supply = 6 V, resistive load, TJ = 25 °C | 2 | ||
| Maximum rate of rise of off-state voltage | dV/dt | 500 | V/μs | TJ = TJ max., linear to 80 °C, VDRM = Rated, Rg-k = Open | 2 | ||
| Maximum rate of rise of turned-on current | dI/dt | 150 | A/μs | 2 | |||
| Maximum peak gate power | PGM | 8 | W | 2 | |||
| Maximum average gate power | PG(AV) | 2 | W | 2 | |||
| Maximum peak positive gate current | +IGM | 1.5 | A | 2 | |||
| Maximum peak negative gate voltage | -VGM | 10 | V | 2 | |||
| Maximum required DC gate current to trigger | IGT | 60 | mA | Anode supply = 6 V, resistive load, TJ = -10 °C | 2 | ||
| Maximum required DC gate current to trigger | IGT | 45 | mA | Anode supply = 6 V, resistive load, TJ = 25 °C | 2 | ||
| Maximum required DC gate current to trigger | IGT | 20 | mA | Anode supply = 6 V, resistive load, TJ = 125 °C | 2 | ||
| Maximum required DC gate voltage to trigger | VGT | 2.5 | V | Anode supply = 6 V, resistive load, TJ = -10 °C | 2 | ||
| Maximum required DC gate voltage to trigger | VGT | 2 | V | Anode supply = 6 V, resistive load, TJ = 25 °C | 2 | ||
| Maximum required DC gate voltage to trigger | VGT | 1 | V | Anode supply = 6 V, resistive load, TJ = 125 °C | 2 | ||
| Maximum DC gate voltage not to trigger | VGD | 0.25 | V | TJ = 125 °C, VDRM = Rated value | 2 | ||
| Maximum DC gate current not to trigger | IGD | 2 | mA | 2 | |||
| Typical turn-on time | tgt | 0.9 | µs | TJ = 25 °C | 2 | ||
| Typical reverse recovery time | trr | 4 | µs | TJ = 125 °C | 2 | ||
| Typical turn-off time | tq | 110 | µs | 2 | |||
| Maximum junction and storage temperature range | TJ, TStg | -40 | 125 | °C | 3 | ||
| Maximum thermal resistance, junction to case | RthJC | 1.1 | °C/W | DC operation | 3 | ||
| Maximum thermal resistance, junction to ambient | RthJA | 62 | °C/W | 3 | |||
| Typical thermal resistance, case to heatsink | RthCS | 0.5 | °C/W | Mounting surface, smooth and greased | 3 |
CAD (KiCad official)
- Symbol:
VS-25TTS12-M3 - Footprint:
Package_TO_SOT_THT:TO-220-3_Vertical - 3D model: TO-220AB-3 (KiCad packages3D, STEP)
- 3D model files:
vs-25tts12-m3-etched.step/vs-25tts12-m3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);vs-25tts12-m3.step/vs-25tts12-m3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (7 pp, sha256
06ca04f9624c67c0, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).