component

VNL5050S5TR-E

Public Made by Adom

by adom

STMicroelectronics AC-DC Controllers and Regulators, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs vnl5050s5tr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json vnl5050s5tr-e: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md vnl5050s5tr-e: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
vnl5050s5tr-e-etched.fit.json vnl5050s5tr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
vnl5050s5tr-e-etched.glb vnl5050s5tr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
vnl5050s5tr-e-etched.step vnl5050s5tr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
vnl5050s5tr-e.glb Publish 0.1.0 · Ray
vnl5050s5tr-e.kicad_mod Publish 0.1.0 · Ray
vnl5050s5tr-e.kicad_sym Publish 0.1.0 · Ray
vnl5050s5tr-e.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
vnl5050s5tr-e.step Publish 0.1.0 · Ray

VNL5050S5TR-E

STMicroelectronics · AC-DC Controllers and Regulators · SO-8

VNL5050S5TR-E from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SUPPLY VOLTAGE power_in Supply voltage for the signal (logic) part, typically 5 V. Feeds the internal SUPPLY/LOGIC block.
2 INPUT input Voltage-controlled input pin with hysteresis, CMOS compatible. Controls the output switch (power MOS) state. DC input current rating -1 to 10 mA. Recommended pull-down to GND through a 10 kΩ resistor if left unused.
3 STATUS output Open-drain digital diagnostic pin (VNL5050S5-E only). Signals fault conditions such as overtemperature or open-load. May be left floating if unused; must NOT be tied to ground. DC status current rating -1 to 10 mA.
4 NC unconnected No internal connection. May be left floating or tied to ground.
5 DRAIN passive Power MOSFET drain. Connects to the load (low-side switch - the other side of the load ties to the battery). Internally clamped VDS (VCLAMP = 41 V), ID up to 19 A. Pins 5 and 8 are internally tied together.
6 SOURCE power_in Power MOSFET source and ground reference for the control section. Pins 6 and 7 are internally tied together and used as the device ground.
7 SOURCE power_in Power MOSFET source and ground reference for the control section. Pins 6 and 7 are internally tied together and used as the device ground.
8 DRAIN passive Power MOSFET drain. Connects to the load (low-side switch). Pins 5 and 8 are internally tied together; recommended to connect all DRAIN pins to a copper pour for thermal dissipation.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • VNL5050S5-E
  • VNL5050S5TR-E
  • VNL5050N3-E
  • VNL5050N3TR-E

CAD (KiCad official)

  • Symbol: VNL5050S5TR-E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: vnl5050s5tr-e-etched.step / vnl5050s5tr-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); vnl5050s5tr-e.step / vnl5050s5tr-e.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
vnl5050s5tr-e.step 122 KB You want the bare part, or you mark your own boards.
vnl5050s5tr-e-etched.step 2.5 MB You want the part with VNL5050S5TR-E already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 603 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (33 pp, sha256 44edd20a5e513e96, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF