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VIPER22ASTR-E

Public Made by Adom

by adom

STMicroelectronics AC-DC Controllers and Regulators, SO-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs viper22astr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 10d ago
README.md viper22astr-e: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 14d ago
viper22astr-e-etched.fit.json viper22astr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viper22astr-e-etched.glb viper22astr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viper22astr-e-etched.step viper22astr-e: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viper22astr-e.glb Publish 0.1.0 · Ray 1mo ago
viper22astr-e.kicad_mod Publish 0.1.0 · Ray 1mo ago
viper22astr-e.kicad_sym Publish 0.1.0 · Ray 1mo ago
viper22astr-e.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
viper22astr-e.step Publish 0.1.0 · Ray 1mo ago

VIPER22ASTR-E

STMicroelectronics · AC-DC Controllers and Regulators · SO-8

VIPER22ASTR-E from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SOURCE power_in Power MOSFET source and circuit ground reference. Pin 1 and pin 2 are internally connected to the same SOURCE node and are the ground return for VDD and FB.
2 SOURCE power_in Power MOSFET source and circuit ground reference (second SOURCE pin, internally tied to pin 1).
3 FB input Feedback input for current-mode PWM regulation. Useful voltage range 0 V to 1 V; the pin is current-sensitive (typically driven by an optocoupler). Peak drain current is defined by IFB; shorting FB to SOURCE yields the peak current limit IDlim (typ 0.7 A). Absolute-max IFB = 3 mA; internal input impedance ~1.2 kΩ.
4 VDD power_in Supply for the internal control circuits. Operating range 9 V to 38 V; absolute max 50 V. VDDon start-up threshold typ 14.5 V (13-16 V), VDDoff undervoltage lockout typ 8 V (7-9 V), overvoltage shutdown VDDovp typ 42 V. During start-up VDD is charged from DRAIN through the internal HV current source; in normal operation it is fed by the auxiliary transformer winding.
5 DRAIN power_in Power MOSFET drain. Also used by the internal high-voltage current source during start-up to charge the external VDD capacitor. BVDSS = 730 V (min); absolute-max VDS(sw) = -0.3 … 730 V; rDS(on) typ 15 Ω. Pins 5, 6, 7, 8 are internally tied to the same DRAIN node and should all be connected together with a large copper area for thermal dissipation.
6 DRAIN power_in Power MOSFET drain (second DRAIN pin, internally tied to pin 5).
7 DRAIN power_in Power MOSFET drain (third DRAIN pin, internally tied to pin 5).
8 DRAIN power_in Power MOSFET drain (fourth DRAIN pin, internally tied to pin 5).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • VIPER22ASTR-E
  • VIPer22AS-E
  • VIPer22ADIP-E

CAD (KiCad official)

  • Symbol: VIPER22ASTR-E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: viper22astr-e-etched.step / viper22astr-e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); viper22astr-e.step / viper22astr-e.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
viper22astr-e.step 122 KB You want the bare part, or you mark your own boards.
viper22astr-e-etched.step 2.2 MB You want the part with VIPER22ASTR-E already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 570 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (21 pp, sha256 9d66a04887088780, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF