# VIPER0PHDTR

**STMicroelectronics** · AC-DC Controllers And Regulators · SO-16

VIPER0PHDTR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground and MOSFET source; pulsed current from Power MOSFET must return through this pin and be connected to same ground plane as SGND with shortest trace. |
| 2 | EAGND | power_in | Error amplifier ground reference; connect directly to negative rail for non-isolated negative output converters, or short to SGND for positive output converters. |
| 3 | VCC | power_in | Controller supply voltage; internal high-voltage current source provides VCC capacitor charging current at startup and during steady-state operation; requires external storage capacitor across VCC-SGND and 0.1 μF bypass capacitor placed close to IC. |
| 4 | SGND | power_in | Signal ground; all groundings of bias components must connect to this pin and be kept separate from pulsed current return path. |
| 5 | FB | input | Direct feedback to inverting input of internal transconductance error amplifier, internally referenced to 1.2 V with respect to EAGND; accepts output voltage information via voltage divider. |
| 6 | COMP | output | Compensation output of internal error amplifier; compensation network placed between this pin and SGND to achieve control loop stability and good dynamic performance. |
| 7 | ON | input | ZPM exit control; IC is reactivated by forcing this pin to SGND for debounce time tDEB_ON; internal pull-up resistor keeps pin at VON level during normal operation. |
| 8 | OFF | input | ZPM enter control; IC enters ZPM by forcing this pin to SGND for debounce time tDEB_OFF; internal pull-up resistor keeps pin at VOFF level during normal operation. |
| 9 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |
| 10 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |
| 11 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |
| 12 | N.C. | unconnected | Not internally connected; must be left floating to maintain safe clearance distance. |
| 13 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |
| 14 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |
| 15 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |
| 16 | DRAIN | output | MOSFET drain; internal high-voltage current source sinks current from this pin to charge VCC capacitor at startup and during steady-state operation; mechanically connected to internal metal PAD for heat dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-16 |
| Category | Power Management (PMIC) |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `VIPER0PHDTR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files: `viper0phdtr-etched.step` / `viper0phdtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `viper0phdtr.step` / `viper0phdtr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8600478613796245504) (36 pp, sha256 `ada84337e66288b0`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/viper0phdtr-datasheet.pdf)